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Implement V_READFIRSTLANE_B32

This commit is contained in:
greggameplayer 2024-08-31 00:39:56 +02:00
parent 4182740384
commit c94ce5d700
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GPG Key ID: DFCB45491D2A00EB
3 changed files with 12 additions and 4 deletions
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2
src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp
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@ -23,7 +23,7 @@ Id EmitQuadShuffle(EmitContext& ctx, Id value, Id index) {
}
Id EmitReadFirstLane(EmitContext& ctx, Id value) {
UNREACHABLE();
return ctx.OpGroupNonUniformBroadcastFirst(ctx.U32[1], SubgroupScope(ctx), value);
}
Id EmitReadLane(EmitContext& ctx, Id value, u32 lane) {

12
src/shader_recompiler/frontend/translate/data_share.cpp
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@ -167,8 +167,16 @@ void Translator::S_BARRIER() {
}
void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
ASSERT(info.stage != Stage::Compute);
SetDst(inst.dst[0], GetSrc(inst.src[0]));
const IR::ScalarReg dst{inst.dst[0].code};
const IR::U32 value{GetSrc(inst.src[0])};
if (ir.GetExec() == ir.Imm1(false)) {
ir.SetScalarReg(dst, value);
} else {
const IR::U32 first_active_value = ir.ReadFirstLane(value);
ir.SetScalarReg(dst, first_active_value);
}
}
void Translator::V_READLANE_B32(const GcnInst& inst) {

2
src/shader_recompiler/ir/opcodes.inc
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@ -340,6 +340,6 @@ OPCODE(ImageAtomicExchange32, U32, Opaq
OPCODE(LaneId, U32, )
OPCODE(WarpId, U32, )
OPCODE(QuadShuffle, U32, U32, U32 )
OPCODE(ReadFirstLane, U32, U32, U32 )
OPCODE(ReadFirstLane, U32, U32, )
OPCODE(ReadLane, U32, U32, U32 )
OPCODE(WriteLane, U32, U32, U32, U32 )