diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp
index c55763c5..898de8b5 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_warp.cpp
@@ -23,7 +23,7 @@ Id EmitQuadShuffle(EmitContext& ctx, Id value, Id index) {
 }
 
 Id EmitReadFirstLane(EmitContext& ctx, Id value) {
-    UNREACHABLE();
+    return ctx.OpGroupNonUniformBroadcastFirst(ctx.U32[1], SubgroupScope(ctx), value);
 }
 
 Id EmitReadLane(EmitContext& ctx, Id value, u32 lane) {
diff --git a/src/shader_recompiler/frontend/translate/data_share.cpp b/src/shader_recompiler/frontend/translate/data_share.cpp
index aa9b49b6..d9cf2f9e 100644
--- a/src/shader_recompiler/frontend/translate/data_share.cpp
+++ b/src/shader_recompiler/frontend/translate/data_share.cpp
@@ -167,8 +167,16 @@ void Translator::S_BARRIER() {
 }
 
 void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
-    ASSERT(info.stage != Stage::Compute);
-    SetDst(inst.dst[0], GetSrc(inst.src[0]));
+    const IR::ScalarReg dst{inst.dst[0].code};
+    const IR::U32 value{GetSrc(inst.src[0])};
+
+    if (ir.GetExec() == ir.Imm1(false)) {
+        ir.SetScalarReg(dst, value);
+    } else {
+        const IR::U32 first_active_value = ir.ReadFirstLane(value);
+
+        ir.SetScalarReg(dst, first_active_value);
+    }
 }
 
 void Translator::V_READLANE_B32(const GcnInst& inst) {
diff --git a/src/shader_recompiler/ir/opcodes.inc b/src/shader_recompiler/ir/opcodes.inc
index 1e33d6d4..40dcfa44 100644
--- a/src/shader_recompiler/ir/opcodes.inc
+++ b/src/shader_recompiler/ir/opcodes.inc
@@ -340,6 +340,6 @@ OPCODE(ImageAtomicExchange32,                               U32,            Opaq
 OPCODE(LaneId,                                              U32,                                                                                            )
 OPCODE(WarpId,                                              U32,                                                                                            )
 OPCODE(QuadShuffle,                                         U32,            U32,            U32                                                             )
-OPCODE(ReadFirstLane,                                       U32,            U32,            U32                                                             )
+OPCODE(ReadFirstLane,                                       U32,            U32,                                                                            )
 OPCODE(ReadLane,                                            U32,            U32,            U32                                                             )
 OPCODE(WriteLane,                                           U32,            U32,            U32,            U32                                             )