Implement V_READFIRSTLANE_B32
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4182740384
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c94ce5d700
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@ -23,7 +23,7 @@ Id EmitQuadShuffle(EmitContext& ctx, Id value, Id index) {
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}
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}
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Id EmitReadFirstLane(EmitContext& ctx, Id value) {
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Id EmitReadFirstLane(EmitContext& ctx, Id value) {
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UNREACHABLE();
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return ctx.OpGroupNonUniformBroadcastFirst(ctx.U32[1], SubgroupScope(ctx), value);
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}
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}
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Id EmitReadLane(EmitContext& ctx, Id value, u32 lane) {
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Id EmitReadLane(EmitContext& ctx, Id value, u32 lane) {
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@ -167,8 +167,16 @@ void Translator::S_BARRIER() {
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}
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}
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void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
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void Translator::V_READFIRSTLANE_B32(const GcnInst& inst) {
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ASSERT(info.stage != Stage::Compute);
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const IR::ScalarReg dst{inst.dst[0].code};
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SetDst(inst.dst[0], GetSrc(inst.src[0]));
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const IR::U32 value{GetSrc(inst.src[0])};
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if (ir.GetExec() == ir.Imm1(false)) {
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ir.SetScalarReg(dst, value);
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} else {
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const IR::U32 first_active_value = ir.ReadFirstLane(value);
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ir.SetScalarReg(dst, first_active_value);
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}
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}
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}
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void Translator::V_READLANE_B32(const GcnInst& inst) {
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void Translator::V_READLANE_B32(const GcnInst& inst) {
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@ -340,6 +340,6 @@ OPCODE(ImageAtomicExchange32, U32, Opaq
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OPCODE(LaneId, U32, )
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OPCODE(LaneId, U32, )
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OPCODE(WarpId, U32, )
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OPCODE(WarpId, U32, )
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OPCODE(QuadShuffle, U32, U32, U32 )
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OPCODE(QuadShuffle, U32, U32, U32 )
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OPCODE(ReadFirstLane, U32, U32, U32 )
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OPCODE(ReadFirstLane, U32, U32, )
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OPCODE(ReadLane, U32, U32, U32 )
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OPCODE(ReadLane, U32, U32, U32 )
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OPCODE(WriteLane, U32, U32, U32, U32 )
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OPCODE(WriteLane, U32, U32, U32, U32 )
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