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gnmdriver/
Author | SHA1 | Date |
---|---|---|
psucien | e8f96b57ed | |
psucien | c9c8673099 | |
psucien | 70bcc26e2d | |
psucien | c752341818 | |
psucien | b2c05dc09d | |
psucien | 3e2ccabb5e | |
psucien | 459083528a | |
psucien | 6fba987df2 |
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@ -472,6 +472,7 @@ set(VIDEO_CORE src/video_core/amdgpu/liverpool.cpp
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src/video_core/amdgpu/pm4_cmds.h
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src/video_core/amdgpu/pm4_cmds.h
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src/video_core/amdgpu/pm4_opcodes.h
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src/video_core/amdgpu/pm4_opcodes.h
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src/video_core/amdgpu/resource.h
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src/video_core/amdgpu/resource.h
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src/video_core/amdgpu/default_context.cpp
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src/video_core/buffer_cache/buffer.cpp
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src/video_core/buffer_cache/buffer.cpp
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src/video_core/buffer_cache/buffer.h
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src/video_core/buffer_cache/buffer.h
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src/video_core/buffer_cache/buffer_cache.cpp
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src/video_core/buffer_cache/buffer_cache.cpp
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@ -55,6 +55,10 @@ static constexpr auto HwInitPacketSize = 0x100u;
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// clang-format off
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// clang-format off
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static constexpr std::array InitSequence{
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static constexpr std::array InitSequence{
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// A fake preamble to mimic context reset sent by FW
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0xc0001200u, 0u, // IT_CLEAR_STATE
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// Actual init state sequence
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x215u, 0u,
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0xc0017600u, 0x215u, 0u,
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@ -94,9 +98,13 @@ static constexpr std::array InitSequence{
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0xc0036900u, 0x295u, 0x100u, 0x100u, 4u,
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0xc0036900u, 0x295u, 0x100u, 0x100u, 4u,
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0xc0017900u, 0x200u, 0xe0000000u,
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0xc0017900u, 0x200u, 0xe0000000u,
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};
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};
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static_assert(InitSequence.size() == 0x73);
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static_assert(InitSequence.size() == 0x73 + 2);
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static constexpr std::array InitSequence175{
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static constexpr std::array InitSequence175{
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// A fake preamble to mimic context reset sent by FW
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0xc0001200u, 0u, // IT_CLEAR_STATE
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// Actual init state sequence
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x215u, 0u,
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0xc0017600u, 0x215u, 0u,
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@ -136,9 +144,13 @@ static constexpr std::array InitSequence175{
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0xc0036900u, 0x295u, 0x100u, 0x100u, 4u,
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0xc0036900u, 0x295u, 0x100u, 0x100u, 4u,
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0xc0017900u, 0x200u, 0xe0000000u,
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0xc0017900u, 0x200u, 0xe0000000u,
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};
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};
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static_assert(InitSequence175.size() == 0x73);
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static_assert(InitSequence175.size() == 0x73 + 2);
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static constexpr std::array InitSequence200{
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static constexpr std::array InitSequence200{
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// A fake preamble to mimic context reset sent by FW
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0xc0001200u, 0u, // IT_CLEAR_STATE
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// Actual init state sequence
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x215u, 0u,
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0xc0017600u, 0x215u, 0u,
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@ -179,9 +191,13 @@ static constexpr std::array InitSequence200{
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0xc0036900u, 0x295u, 0x100u, 0x100u, 4u,
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0xc0036900u, 0x295u, 0x100u, 0x100u, 4u,
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0xc0017900u, 0x200u, 0xe0000000u,
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0xc0017900u, 0x200u, 0xe0000000u,
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};
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};
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static_assert(InitSequence200.size() == 0x76);
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static_assert(InitSequence200.size() == 0x76 + 2);
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static constexpr std::array InitSequence350{
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static constexpr std::array InitSequence350{
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// A fake preamble to mimic context reset sent by FW
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0xc0001200u, 0u, // IT_CLEAR_STATE
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// Actual init state sequence
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x216u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x217u, 0xffffffffu,
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0xc0017600u, 0x215u, 0u,
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0xc0017600u, 0x215u, 0u,
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@ -224,7 +240,7 @@ static constexpr std::array InitSequence350{
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0xc0017900u, 0x200u, 0xe0000000u,
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0xc0017900u, 0x200u, 0xe0000000u,
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0xc0016900u, 0x2aau, 0xffu,
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0xc0016900u, 0x2aau, 0xffu,
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};
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};
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static_assert(InitSequence350.size() == 0x7c);
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static_assert(InitSequence350.size() == 0x7c + 2);
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static constexpr std::array CtxInitSequence{
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static constexpr std::array CtxInitSequence{
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0xc0012800u, 0x80000000u, 0x80000000u,
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0xc0012800u, 0x80000000u, 0x80000000u,
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@ -735,11 +751,11 @@ u32 PS4_SYSV_ABI sceGnmDrawInitDefaultHardwareState(u32* cmdbuf, u32 size) {
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cmdbuf = ClearContextState(cmdbuf);
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cmdbuf = ClearContextState(cmdbuf);
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}
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}
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std::memcpy(cmdbuf, InitSequence.data(), InitSequence.size() * 4);
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std::memcpy(cmdbuf, &InitSequence[2], (InitSequence.size() - 2) * 4);
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cmdbuf += InitSequence.size();
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cmdbuf += InitSequence.size() - 2;
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const auto cmdbuf_left =
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const auto cmdbuf_left =
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HwInitPacketSize - InitSequence.size() - (clear_state ? 0xc : 0) - 1;
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HwInitPacketSize - (InitSequence.size() - 2) - (clear_state ? 0xc : 0) - 1;
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cmdbuf = WriteHeader<PM4ItOpcode::Nop>(cmdbuf, cmdbuf_left);
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cmdbuf = WriteHeader<PM4ItOpcode::Nop>(cmdbuf, cmdbuf_left);
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cmdbuf = WriteBody(cmdbuf, 0u);
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cmdbuf = WriteBody(cmdbuf, 0u);
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@ -757,10 +773,10 @@ u32 PS4_SYSV_ABI sceGnmDrawInitDefaultHardwareState175(u32* cmdbuf, u32 size) {
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}
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}
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cmdbuf = ClearContextState(cmdbuf);
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cmdbuf = ClearContextState(cmdbuf);
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std::memcpy(cmdbuf, InitSequence175.data(), InitSequence175.size() * 4);
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std::memcpy(cmdbuf, &InitSequence175[2], (InitSequence175.size() - 2) * 4);
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cmdbuf += InitSequence175.size();
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cmdbuf += InitSequence175.size() - 2;
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constexpr auto cmdbuf_left = HwInitPacketSize - InitSequence175.size() - 0xc - 1;
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constexpr auto cmdbuf_left = HwInitPacketSize - (InitSequence175.size() - 2) - 0xc - 1;
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WriteTrailingNop<cmdbuf_left>(cmdbuf);
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WriteTrailingNop<cmdbuf_left>(cmdbuf);
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return HwInitPacketSize;
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return HwInitPacketSize;
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@ -778,11 +794,11 @@ u32 PS4_SYSV_ABI sceGnmDrawInitDefaultHardwareState200(u32* cmdbuf, u32 size) {
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cmdbuf = ClearContextState(cmdbuf);
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cmdbuf = ClearContextState(cmdbuf);
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}
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}
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std::memcpy(cmdbuf, InitSequence200.data(), InitSequence200.size() * 4);
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std::memcpy(cmdbuf, &InitSequence200[2], (InitSequence200.size() - 2) * 4);
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cmdbuf += InitSequence200.size();
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cmdbuf += InitSequence200.size() - 2;
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const auto cmdbuf_left =
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const auto cmdbuf_left =
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HwInitPacketSize - InitSequence200.size() - (clear_state ? 0xc : 0) - 1;
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HwInitPacketSize - (InitSequence200.size() - 2) - (clear_state ? 0xc : 0) - 1;
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cmdbuf = WriteHeader<PM4ItOpcode::Nop>(cmdbuf, cmdbuf_left);
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cmdbuf = WriteHeader<PM4ItOpcode::Nop>(cmdbuf, cmdbuf_left);
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cmdbuf = WriteBody(cmdbuf, 0u);
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cmdbuf = WriteBody(cmdbuf, 0u);
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@ -804,11 +820,11 @@ u32 PS4_SYSV_ABI sceGnmDrawInitDefaultHardwareState350(u32* cmdbuf, u32 size) {
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cmdbuf = ClearContextState(cmdbuf);
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cmdbuf = ClearContextState(cmdbuf);
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}
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}
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std::memcpy(cmdbuf, InitSequence350.data(), InitSequence350.size() * 4);
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std::memcpy(cmdbuf, &InitSequence350[2], (InitSequence350.size() - 2) * 4);
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cmdbuf += InitSequence350.size();
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cmdbuf += InitSequence350.size() - 2;
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const auto cmdbuf_left =
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const auto cmdbuf_left =
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HwInitPacketSize - InitSequence350.size() - (clear_state ? 0xc : 0) - 1;
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HwInitPacketSize - (InitSequence350.size() - 2) - (clear_state ? 0xc : 0) - 1;
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cmdbuf = WriteHeader<PM4ItOpcode::Nop>(cmdbuf, cmdbuf_left);
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cmdbuf = WriteHeader<PM4ItOpcode::Nop>(cmdbuf, cmdbuf_left);
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cmdbuf = WriteBody(cmdbuf, 0u);
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cmdbuf = WriteBody(cmdbuf, 0u);
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@ -1743,7 +1759,7 @@ s32 PS4_SYSV_ABI sceGnmSetVsShader(u32* cmdbuf, u32 size, const u32* vs_regs, u3
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return -1;
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return -1;
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}
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}
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const u32 var = shader_modifier == 0 ? vs_regs[2] : (vs_regs[2] & 0xfcfffc3f | shader_modifier);
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const u32 var = shader_modifier == 0 ? vs_regs[2] : (vs_regs[2] & 0xfcfffc3f) | shader_modifier;
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cmdbuf = PM4CmdSetData::SetShReg(cmdbuf, 0x48u, vs_regs[0], 0u); // SPI_SHADER_PGM_LO_VS
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cmdbuf = PM4CmdSetData::SetShReg(cmdbuf, 0x48u, vs_regs[0], 0u); // SPI_SHADER_PGM_LO_VS
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cmdbuf = PM4CmdSetData::SetShReg(cmdbuf, 0x4au, var, vs_regs[3]); // SPI_SHADER_PGM_RSRC1_VS
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cmdbuf = PM4CmdSetData::SetShReg(cmdbuf, 0x4au, var, vs_regs[3]); // SPI_SHADER_PGM_RSRC1_VS
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cmdbuf = PM4CmdSetData::SetContextReg(cmdbuf, 0x207u, vs_regs[6]); // PA_CL_VS_OUT_CNTL
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cmdbuf = PM4CmdSetData::SetContextReg(cmdbuf, 0x207u, vs_regs[6]); // PA_CL_VS_OUT_CNTL
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@ -185,14 +185,16 @@ s32 PS4_SYSV_ABI sceVideoOutGetFlipStatus(s32 handle, FlipStatus* status) {
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return ORBIS_VIDEO_OUT_ERROR_INVALID_HANDLE;
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return ORBIS_VIDEO_OUT_ERROR_INVALID_HANDLE;
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}
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}
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std::unique_lock lock{port->port_mutex};
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{
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*status = port->flip_status;
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std::unique_lock lock{port->port_mutex};
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*status = port->flip_status;
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}
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LOG_INFO(Lib_VideoOut,
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LOG_TRACE(Lib_VideoOut,
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"count = {}, processTime = {}, tsc = {}, submitTsc = {}, flipArg = {}, gcQueueNum = "
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"count = {}, processTime = {}, tsc = {}, submitTsc = {}, flipArg = {}, gcQueueNum = "
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"{}, flipPendingNum = {}, currentBuffer = {}",
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"{}, flipPendingNum = {}, currentBuffer = {}",
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status->count, status->processTime, status->tsc, status->submitTsc, status->flipArg,
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status->count, status->processTime, status->tsc, status->submitTsc, status->flipArg,
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status->gcQueueNum, status->flipPendingNum, status->currentBuffer);
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status->gcQueueNum, status->flipPendingNum, status->currentBuffer);
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return ORBIS_OK;
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return ORBIS_OK;
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}
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}
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@ -179,6 +179,7 @@ void DefineEntryPoint(const IR::Program& program, EmitContext& ctx, Id main) {
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spv::ExecutionModel execution_model{};
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spv::ExecutionModel execution_model{};
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ctx.AddCapability(spv::Capability::Image1D);
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ctx.AddCapability(spv::Capability::Image1D);
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ctx.AddCapability(spv::Capability::Sampled1D);
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ctx.AddCapability(spv::Capability::Sampled1D);
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ctx.AddCapability(spv::Capability::ImageQuery);
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if (info.uses_fp16) {
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if (info.uses_fp16) {
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ctx.AddCapability(spv::Capability::Float16);
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ctx.AddCapability(spv::Capability::Float16);
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ctx.AddCapability(spv::Capability::Int16);
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ctx.AddCapability(spv::Capability::Int16);
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@ -405,6 +405,10 @@ spv::ImageFormat GetFormat(const AmdGpu::Image& image) {
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image.GetNumberFmt() == AmdGpu::NumberFormat::Float) {
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image.GetNumberFmt() == AmdGpu::NumberFormat::Float) {
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return spv::ImageFormat::Rg16f;
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return spv::ImageFormat::Rg16f;
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}
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}
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format16_16 &&
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image.GetNumberFmt() == AmdGpu::NumberFormat::Snorm) {
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return spv::ImageFormat::Rg16Snorm;
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}
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format8_8 &&
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format8_8 &&
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image.GetNumberFmt() == AmdGpu::NumberFormat::Unorm) {
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image.GetNumberFmt() == AmdGpu::NumberFormat::Unorm) {
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return spv::ImageFormat::Rg8;
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return spv::ImageFormat::Rg8;
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@ -21,8 +21,13 @@ struct Compare {
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}
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}
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};
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};
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static IR::Condition MakeCondition(Opcode opcode) {
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static IR::Condition MakeCondition(const GcnInst& inst) {
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switch (opcode) {
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if (inst.IsCmpx()) {
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ASSERT(inst.opcode == Opcode::V_CMPX_NE_U32);
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return IR::Condition::Execnz;
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}
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switch (inst.opcode) {
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case Opcode::S_CBRANCH_SCC0:
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case Opcode::S_CBRANCH_SCC0:
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return IR::Condition::Scc0;
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return IR::Condition::Scc0;
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case Opcode::S_CBRANCH_SCC1:
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case Opcode::S_CBRANCH_SCC1:
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@ -37,7 +42,6 @@ static IR::Condition MakeCondition(Opcode opcode) {
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return IR::Condition::Execnz;
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return IR::Condition::Execnz;
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case Opcode::S_AND_SAVEEXEC_B64:
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case Opcode::S_AND_SAVEEXEC_B64:
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case Opcode::S_ANDN2_B64:
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case Opcode::S_ANDN2_B64:
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case Opcode::V_CMPX_NE_U32:
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return IR::Condition::Execnz;
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return IR::Condition::Execnz;
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default:
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default:
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return IR::Condition::True;
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return IR::Condition::True;
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@ -94,7 +98,8 @@ void CFG::EmitDivergenceLabels() {
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// While this instruction does not save EXEC it is often used paired
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// While this instruction does not save EXEC it is often used paired
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// with SAVEEXEC to mask the threads that didn't pass the condition
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// with SAVEEXEC to mask the threads that didn't pass the condition
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// of initial branch.
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// of initial branch.
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inst.opcode == Opcode::S_ANDN2_B64 || inst.opcode == Opcode::V_CMPX_NE_U32;
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(inst.opcode == Opcode::S_ANDN2_B64 && inst.dst[0].field == OperandField::ExecLo) ||
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inst.opcode == Opcode::V_CMPX_NE_U32;
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};
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};
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const auto is_close_scope = [](const GcnInst& inst) {
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const auto is_close_scope = [](const GcnInst& inst) {
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// Closing an EXEC scope can be either a branch instruction
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// Closing an EXEC scope can be either a branch instruction
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@ -104,7 +109,8 @@ void CFG::EmitDivergenceLabels() {
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// Sometimes compiler might insert instructions between the SAVEEXEC and the branch.
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// Sometimes compiler might insert instructions between the SAVEEXEC and the branch.
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// Those instructions need to be wrapped in the condition as well so allow branch
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// Those instructions need to be wrapped in the condition as well so allow branch
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// as end scope instruction.
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// as end scope instruction.
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inst.opcode == Opcode::S_CBRANCH_EXECZ || inst.opcode == Opcode::S_ANDN2_B64;
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inst.opcode == Opcode::S_CBRANCH_EXECZ ||
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(inst.opcode == Opcode::S_ANDN2_B64 && inst.dst[0].field == OperandField::ExecLo);
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};
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};
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// Since we will be adding new labels, avoid iterating those as well.
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// Since we will be adding new labels, avoid iterating those as well.
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@ -171,7 +177,7 @@ void CFG::EmitBlocks() {
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block->begin_index = GetIndex(start);
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block->begin_index = GetIndex(start);
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block->end_index = end_index;
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block->end_index = end_index;
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block->end_inst = end_inst;
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block->end_inst = end_inst;
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block->cond = MakeCondition(end_inst.opcode);
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block->cond = MakeCondition(end_inst);
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blocks.insert(*block);
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blocks.insert(*block);
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}
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}
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}
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}
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@ -47,4 +47,18 @@ bool GcnInst::IsConditionalBranch() const {
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return false;
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return false;
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}
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}
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bool GcnInst::IsCmpx() const {
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if ((opcode >= Opcode::V_CMPX_F_F32 && opcode <= Opcode::V_CMPX_T_F32) ||
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(opcode >= Opcode::V_CMPX_F_F64 && opcode <= Opcode::V_CMPX_T_F64) ||
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(opcode >= Opcode::V_CMPSX_F_F32 && opcode <= Opcode::V_CMPSX_T_F32) ||
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(opcode >= Opcode::V_CMPSX_F_F64 && opcode <= Opcode::V_CMPSX_T_F64) ||
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(opcode >= Opcode::V_CMPX_F_I32 && opcode <= Opcode::V_CMPX_CLASS_F32) ||
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(opcode >= Opcode::V_CMPX_F_I64 && opcode <= Opcode::V_CMPX_CLASS_F64) ||
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(opcode >= Opcode::V_CMPX_F_U32 && opcode <= Opcode::V_CMPX_T_U32) ||
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||||||
|
(opcode >= Opcode::V_CMPX_F_U64 && opcode <= Opcode::V_CMPX_T_U64)) {
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
} // namespace Shader::Gcn
|
} // namespace Shader::Gcn
|
||||||
|
|
|
@ -203,6 +203,7 @@ struct GcnInst {
|
||||||
bool IsUnconditionalBranch() const;
|
bool IsUnconditionalBranch() const;
|
||||||
bool IsConditionalBranch() const;
|
bool IsConditionalBranch() const;
|
||||||
bool IsFork() const;
|
bool IsFork() const;
|
||||||
|
bool IsCmpx() const;
|
||||||
};
|
};
|
||||||
|
|
||||||
} // namespace Shader::Gcn
|
} // namespace Shader::Gcn
|
||||||
|
|
|
@ -280,6 +280,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
|
||||||
return V_CMP_U32(ConditionOp::GT, true, false, inst);
|
return V_CMP_U32(ConditionOp::GT, true, false, inst);
|
||||||
case Opcode::V_CMP_LT_I32:
|
case Opcode::V_CMP_LT_I32:
|
||||||
return V_CMP_U32(ConditionOp::LT, true, false, inst);
|
return V_CMP_U32(ConditionOp::LT, true, false, inst);
|
||||||
|
case Opcode::V_CMPX_GT_I32:
|
||||||
|
return V_CMP_U32(ConditionOp::GT, true, true, inst);
|
||||||
case Opcode::V_CMPX_LT_I32:
|
case Opcode::V_CMPX_LT_I32:
|
||||||
return V_CMP_U32(ConditionOp::LT, true, true, inst);
|
return V_CMP_U32(ConditionOp::LT, true, true, inst);
|
||||||
case Opcode::V_CMPX_F_U32:
|
case Opcode::V_CMPX_F_U32:
|
||||||
|
|
|
@ -246,10 +246,7 @@ public:
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
// Samplers with different bindings might still be the same.
|
// Samplers with different bindings might still be the same.
|
||||||
const auto old_sharp =
|
return existing.GetSsharp(info) == desc.GetSsharp(info);
|
||||||
info.ReadUd<AmdGpu::Sampler>(existing.sgpr_base, existing.dword_offset);
|
|
||||||
const auto new_sharp = info.ReadUd<AmdGpu::Sampler>(desc.sgpr_base, desc.dword_offset);
|
|
||||||
return old_sharp == new_sharp;
|
|
||||||
})};
|
})};
|
||||||
return index;
|
return index;
|
||||||
}
|
}
|
||||||
|
|
|
@ -0,0 +1,55 @@
|
||||||
|
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
|
||||||
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
|
#include "common/types.h"
|
||||||
|
#include "video_core/amdgpu/liverpool.h"
|
||||||
|
|
||||||
|
#include <array>
|
||||||
|
|
||||||
|
namespace AmdGpu {
|
||||||
|
|
||||||
|
// The following values are taken from fpPS4:
|
||||||
|
// https://github.com/red-prig/fpPS4/blob/436b43064be4c78229500f3d3c054fc76639247d/chip/pm4_pfp.pas#L410
|
||||||
|
//
|
||||||
|
static constexpr std::array reg_array_default{
|
||||||
|
0x00000000u, 0x80000000u, 0x40004000u, 0xdeadbeefu, 0x00000000u, 0x40004000u, 0x00000000u,
|
||||||
|
0x40004000u, 0x00000000u, 0x40004000u, 0x00000000u, 0x40004000u, 0xaa99aaaau, 0x00000000u,
|
||||||
|
0xdeadbeefu, 0xdeadbeefu, 0x80000000u, 0x40004000u, 0x00000000u, 0x00000000u, 0x80000000u,
|
||||||
|
0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u,
|
||||||
|
0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u,
|
||||||
|
0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u,
|
||||||
|
0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u, 0x40004000u, 0x80000000u,
|
||||||
|
0x40004000u, 0x80000000u, 0x40004000u, 0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u,
|
||||||
|
0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u,
|
||||||
|
0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u,
|
||||||
|
0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u,
|
||||||
|
0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u, 0x00000000u, 0x3f800000u,
|
||||||
|
0x2a00161au,
|
||||||
|
};
|
||||||
|
|
||||||
|
void Liverpool::Regs::SetDefaults() {
|
||||||
|
std::memset(reg_array.data(), 0, reg_array.size() * sizeof(u32));
|
||||||
|
|
||||||
|
std::memcpy(®_array[ContextRegWordOffset + 0x80], reg_array_default.data(),
|
||||||
|
reg_array_default.size() * sizeof(u32));
|
||||||
|
|
||||||
|
// Individual context regs values
|
||||||
|
reg_array[ContextRegWordOffset + 0x000d] = 0x40004000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x01b6] = 0x00000002u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x0204] = 0x00090000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x0205] = 0x00000004u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x0295] = 0x00000100u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x0296] = 0x00000080u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x0297] = 0x00000002u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x02aa] = 0x00001000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x02f7] = 0x00001000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x02f9] = 0x00000005u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x02fa] = 0x3f800000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x02fb] = 0x3f800000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x02fc] = 0x3f800000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x02fd] = 0x3f800000u;
|
||||||
|
reg_array[ContextRegWordOffset + 0x0316] = 0x0000000eu;
|
||||||
|
reg_array[ContextRegWordOffset + 0x0317] = 0x00000010u;
|
||||||
|
}
|
||||||
|
|
||||||
|
} // namespace AmdGpu
|
|
@ -216,6 +216,7 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case PM4ItOpcode::ClearState: {
|
case PM4ItOpcode::ClearState: {
|
||||||
|
regs.SetDefaults();
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case PM4ItOpcode::SetConfigReg: {
|
case PM4ItOpcode::SetConfigReg: {
|
||||||
|
|
|
@ -1017,6 +1017,8 @@ struct Liverpool {
|
||||||
}
|
}
|
||||||
return nullptr;
|
return nullptr;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void SetDefaults();
|
||||||
};
|
};
|
||||||
|
|
||||||
Regs regs{};
|
Regs regs{};
|
||||||
|
|
|
@ -38,9 +38,9 @@ struct UniqueBuffer {
|
||||||
UniqueBuffer& operator=(const UniqueBuffer&) = delete;
|
UniqueBuffer& operator=(const UniqueBuffer&) = delete;
|
||||||
|
|
||||||
UniqueBuffer(UniqueBuffer&& other)
|
UniqueBuffer(UniqueBuffer&& other)
|
||||||
: buffer{std::exchange(other.buffer, VK_NULL_HANDLE)},
|
: allocator{std::exchange(other.allocator, VK_NULL_HANDLE)},
|
||||||
allocator{std::exchange(other.allocator, VK_NULL_HANDLE)},
|
allocation{std::exchange(other.allocation, VK_NULL_HANDLE)},
|
||||||
allocation{std::exchange(other.allocation, VK_NULL_HANDLE)} {}
|
buffer{std::exchange(other.buffer, VK_NULL_HANDLE)} {}
|
||||||
UniqueBuffer& operator=(UniqueBuffer&& other) {
|
UniqueBuffer& operator=(UniqueBuffer&& other) {
|
||||||
buffer = std::exchange(other.buffer, VK_NULL_HANDLE);
|
buffer = std::exchange(other.buffer, VK_NULL_HANDLE);
|
||||||
allocator = std::exchange(other.allocator, VK_NULL_HANDLE);
|
allocator = std::exchange(other.allocator, VK_NULL_HANDLE);
|
||||||
|
|
|
@ -274,6 +274,7 @@ bool Instance::CreateDevice() {
|
||||||
.independentBlend = features.independentBlend,
|
.independentBlend = features.independentBlend,
|
||||||
.geometryShader = features.geometryShader,
|
.geometryShader = features.geometryShader,
|
||||||
.logicOp = features.logicOp,
|
.logicOp = features.logicOp,
|
||||||
|
.depthBiasClamp = features.depthBiasClamp,
|
||||||
.multiViewport = features.multiViewport,
|
.multiViewport = features.multiViewport,
|
||||||
.samplerAnisotropy = features.samplerAnisotropy,
|
.samplerAnisotropy = features.samplerAnisotropy,
|
||||||
.fragmentStoresAndAtomics = features.fragmentStoresAndAtomics,
|
.fragmentStoresAndAtomics = features.fragmentStoresAndAtomics,
|
||||||
|
|
|
@ -138,8 +138,8 @@ void Rasterizer::BeginRendering() {
|
||||||
using StencilFormat = AmdGpu::Liverpool::DepthBuffer::StencilFormat;
|
using StencilFormat = AmdGpu::Liverpool::DepthBuffer::StencilFormat;
|
||||||
if (regs.depth_buffer.Address() != 0 &&
|
if (regs.depth_buffer.Address() != 0 &&
|
||||||
((regs.depth_control.depth_enable && regs.depth_buffer.z_info.format != ZFormat::Invalid) ||
|
((regs.depth_control.depth_enable && regs.depth_buffer.z_info.format != ZFormat::Invalid) ||
|
||||||
regs.depth_control.stencil_enable &&
|
(regs.depth_control.stencil_enable &&
|
||||||
regs.depth_buffer.stencil_info.format != StencilFormat::Invalid)) {
|
regs.depth_buffer.stencil_info.format != StencilFormat::Invalid))) {
|
||||||
const auto htile_address = regs.depth_htile_data_base.GetAddress();
|
const auto htile_address = regs.depth_htile_data_base.GetAddress();
|
||||||
const bool is_clear = regs.depth_render_control.depth_clear_enable ||
|
const bool is_clear = regs.depth_render_control.depth_clear_enable ||
|
||||||
texture_cache.IsMetaCleared(htile_address);
|
texture_cache.IsMetaCleared(htile_address);
|
||||||
|
|
|
@ -43,9 +43,9 @@ struct UniqueImage {
|
||||||
UniqueImage& operator=(const UniqueImage&) = delete;
|
UniqueImage& operator=(const UniqueImage&) = delete;
|
||||||
|
|
||||||
UniqueImage(UniqueImage&& other)
|
UniqueImage(UniqueImage&& other)
|
||||||
: image{std::exchange(other.image, VK_NULL_HANDLE)},
|
: allocator{std::exchange(other.allocator, VK_NULL_HANDLE)},
|
||||||
allocator{std::exchange(other.allocator, VK_NULL_HANDLE)},
|
allocation{std::exchange(other.allocation, VK_NULL_HANDLE)},
|
||||||
allocation{std::exchange(other.allocation, VK_NULL_HANDLE)} {}
|
image{std::exchange(other.image, VK_NULL_HANDLE)} {}
|
||||||
UniqueImage& operator=(UniqueImage&& other) {
|
UniqueImage& operator=(UniqueImage&& other) {
|
||||||
image = std::exchange(other.image, VK_NULL_HANDLE);
|
image = std::exchange(other.image, VK_NULL_HANDLE);
|
||||||
allocator = std::exchange(other.allocator, VK_NULL_HANDLE);
|
allocator = std::exchange(other.allocator, VK_NULL_HANDLE);
|
||||||
|
|
|
@ -2,6 +2,7 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||||
|
|
||||||
#include "common/logging/log.h"
|
#include "common/logging/log.h"
|
||||||
|
#include "video_core/amdgpu/resource.h"
|
||||||
#include "video_core/renderer_vulkan/liverpool_to_vk.h"
|
#include "video_core/renderer_vulkan/liverpool_to_vk.h"
|
||||||
#include "video_core/renderer_vulkan/vk_instance.h"
|
#include "video_core/renderer_vulkan/vk_instance.h"
|
||||||
#include "video_core/texture_cache/image.h"
|
#include "video_core/texture_cache/image.h"
|
||||||
|
@ -110,7 +111,7 @@ ImageViewInfo::ImageViewInfo(const AmdGpu::Liverpool::DepthBuffer& depth_buffer,
|
||||||
|
|
||||||
ImageView::ImageView(const Vulkan::Instance& instance, const ImageViewInfo& info_, Image& image,
|
ImageView::ImageView(const Vulkan::Instance& instance, const ImageViewInfo& info_, Image& image,
|
||||||
ImageId image_id_, std::optional<vk::ImageUsageFlags> usage_override /*= {}*/)
|
ImageId image_id_, std::optional<vk::ImageUsageFlags> usage_override /*= {}*/)
|
||||||
: info{info_}, image_id{image_id_} {
|
: image_id{image_id_}, info{info_} {
|
||||||
vk::ImageViewUsageCreateInfo usage_ci{};
|
vk::ImageViewUsageCreateInfo usage_ci{};
|
||||||
if (usage_override) {
|
if (usage_override) {
|
||||||
usage_ci.usage = usage_override.value();
|
usage_ci.usage = usage_override.value();
|
||||||
|
|
|
@ -342,12 +342,6 @@ TileManager::ScratchBuffer TileManager::AllocBuffer(u32 size, bool is_storage /*
|
||||||
.usage = usage,
|
.usage = usage,
|
||||||
};
|
};
|
||||||
|
|
||||||
#ifdef __APPLE__
|
|
||||||
// Fix for detiler artifacts on macOS
|
|
||||||
const bool is_large_buffer = true;
|
|
||||||
#else
|
|
||||||
const bool is_large_buffer = size > 128_MB;
|
|
||||||
#endif
|
|
||||||
VmaAllocationCreateInfo alloc_info{
|
VmaAllocationCreateInfo alloc_info{
|
||||||
.flags = !is_storage ? VMA_ALLOCATION_CREATE_HOST_ACCESS_ALLOW_TRANSFER_INSTEAD_BIT |
|
.flags = !is_storage ? VMA_ALLOCATION_CREATE_HOST_ACCESS_ALLOW_TRANSFER_INSTEAD_BIT |
|
||||||
VMA_ALLOCATION_CREATE_HOST_ACCESS_SEQUENTIAL_WRITE_BIT
|
VMA_ALLOCATION_CREATE_HOST_ACCESS_SEQUENTIAL_WRITE_BIT
|
||||||
|
@ -462,7 +456,6 @@ std::optional<vk::Buffer> TileManager::TryDetile(Image& image) {
|
||||||
(m > 0 ? params.sizes[m - 1] : 0);
|
(m > 0 ? params.sizes[m - 1] : 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
auto pitch = image.info.pitch;
|
|
||||||
cmdbuf.pushConstants(*detiler->pl_layout, vk::ShaderStageFlagBits::eCompute, 0u, sizeof(params),
|
cmdbuf.pushConstants(*detiler->pl_layout, vk::ShaderStageFlagBits::eCompute, 0u, sizeof(params),
|
||||||
¶ms);
|
¶ms);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue