recompiler: trivial missing ops (VALU OR and SALU LE, GE) added
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@ -228,6 +228,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_AND_B32:
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translator.V_AND_B32(inst);
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break;
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case Opcode::V_OR_B32:
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translator.V_OR_B32(inst);
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break;
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case Opcode::V_LSHLREV_B32:
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translator.V_LSHLREV_B32(inst);
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break;
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@ -318,6 +321,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CMP_EQ_I32:
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translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
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break;
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case Opcode::V_CMP_LE_I32:
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translator.V_CMP_U32(ConditionOp::LE, true, false, inst);
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break;
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case Opcode::V_CMP_NE_U32:
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translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
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break;
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@ -378,6 +384,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::S_CMP_GT_I32:
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translator.S_CMP(ConditionOp::GT, true, inst);
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break;
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case Opcode::S_CMP_GE_I32:
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translator.S_CMP(ConditionOp::GE, true, inst);
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break;
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case Opcode::S_CMP_EQ_I32:
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translator.S_CMP(ConditionOp::EQ, true, inst);
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break;
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@ -62,6 +62,7 @@ public:
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void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
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void V_MUL_F32(const GcnInst& inst);
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void V_CNDMASK_B32(const GcnInst& inst);
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void V_OR_B32(const GcnInst& inst);
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void V_AND_B32(const GcnInst& inst);
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void V_LSHLREV_B32(const GcnInst& inst);
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void V_ADD_I32(const GcnInst& inst);
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@ -50,6 +50,13 @@ void Translator::V_CNDMASK_B32(const GcnInst& inst) {
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ir.SetVectorReg(dst_reg, IR::U32F32{result});
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}
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void Translator::V_OR_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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ir.SetVectorReg(dst_reg, ir.BitwiseOr(src0, src1));
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}
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void Translator::V_AND_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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