From cb2cf7d93cdcbf9646a6806f0b2661344bae8771 Mon Sep 17 00:00:00 2001
From: psucien <bad_cast@protonmail.com>
Date: Mon, 10 Jun 2024 23:49:23 +0200
Subject: [PATCH] recompiler: trivial missing ops (VALU OR and SALU LE, GE)
 added

---
 src/shader_recompiler/frontend/translate/translate.cpp  | 9 +++++++++
 src/shader_recompiler/frontend/translate/translate.h    | 1 +
 src/shader_recompiler/frontend/translate/vector_alu.cpp | 7 +++++++
 3 files changed, 17 insertions(+)

diff --git a/src/shader_recompiler/frontend/translate/translate.cpp b/src/shader_recompiler/frontend/translate/translate.cpp
index c0ddf4ae..a32cde39 100644
--- a/src/shader_recompiler/frontend/translate/translate.cpp
+++ b/src/shader_recompiler/frontend/translate/translate.cpp
@@ -228,6 +228,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
         case Opcode::V_AND_B32:
             translator.V_AND_B32(inst);
             break;
+        case Opcode::V_OR_B32:
+            translator.V_OR_B32(inst);
+            break;
         case Opcode::V_LSHLREV_B32:
             translator.V_LSHLREV_B32(inst);
             break;
@@ -318,6 +321,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
         case Opcode::V_CMP_EQ_I32:
             translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
             break;
+        case Opcode::V_CMP_LE_I32:
+            translator.V_CMP_U32(ConditionOp::LE, true, false, inst);
+            break;
         case Opcode::V_CMP_NE_U32:
             translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
             break;
@@ -378,6 +384,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
         case Opcode::S_CMP_GT_I32:
             translator.S_CMP(ConditionOp::GT, true, inst);
             break;
+        case Opcode::S_CMP_GE_I32:
+            translator.S_CMP(ConditionOp::GE, true, inst);
+            break;
         case Opcode::S_CMP_EQ_I32:
             translator.S_CMP(ConditionOp::EQ, true, inst);
             break;
diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h
index a8964fc9..64d6d7f0 100644
--- a/src/shader_recompiler/frontend/translate/translate.h
+++ b/src/shader_recompiler/frontend/translate/translate.h
@@ -62,6 +62,7 @@ public:
     void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
     void V_MUL_F32(const GcnInst& inst);
     void V_CNDMASK_B32(const GcnInst& inst);
+    void V_OR_B32(const GcnInst& inst);
     void V_AND_B32(const GcnInst& inst);
     void V_LSHLREV_B32(const GcnInst& inst);
     void V_ADD_I32(const GcnInst& inst);
diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp
index dbd9471f..2281a038 100644
--- a/src/shader_recompiler/frontend/translate/vector_alu.cpp
+++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp
@@ -50,6 +50,13 @@ void Translator::V_CNDMASK_B32(const GcnInst& inst) {
     ir.SetVectorReg(dst_reg, IR::U32F32{result});
 }
 
+void Translator::V_OR_B32(const GcnInst& inst) {
+    const IR::U32 src0{GetSrc(inst.src[0])};
+    const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
+    const IR::VectorReg dst_reg{inst.dst[0].code};
+    ir.SetVectorReg(dst_reg, ir.BitwiseOr(src0, src1));
+}
+
 void Translator::V_AND_B32(const GcnInst& inst) {
     const IR::U32 src0{GetSrc(inst.src[0])};
     const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};