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clang format fix

This commit is contained in:
georgemoralis 2024-07-15 14:18:28 +03:00
parent 58d1cbd9b7
commit ba0be91c73
4 changed files with 8 additions and 6 deletions
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2
src/core/libraries/kernel/event_flag/event_flag_obj.h
View File

@ -20,7 +20,7 @@ public:
EventFlagInternal(const std::string& name, ThreadMode thread_mode, QueueMode queue_mode,
uint64_t bits)
: m_name(name), m_thread_mode(thread_mode), m_queue_mode(queue_mode), m_bits(bits) {};
: m_name(name), m_thread_mode(thread_mode), m_queue_mode(queue_mode), m_bits(bits){};
int Wait(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result, u32* ptr_micros);
int Poll(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result);

4
src/shader_recompiler/ir/breadth_first_search.h
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@ -12,8 +12,8 @@
namespace Shader::IR {
template <typename Pred>
auto BreadthFirstSearch(const Value& value,
Pred&& pred) -> std::invoke_result_t<Pred, const Inst*> {
auto BreadthFirstSearch(const Value& value, Pred&& pred)
-> std::invoke_result_t<Pred, const Inst*> {
if (value.IsImmediate()) {
// Nothing to do with immediates
return std::nullopt;

2
src/shader_recompiler/ir/opcodes.h
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@ -52,7 +52,7 @@ constexpr Type F64x2{Type::F64x2};
constexpr Type F64x3{Type::F64x3};
constexpr Type F64x4{Type::F64x4};
constexpr OpcodeMeta META_TABLE[] {
constexpr OpcodeMeta META_TABLE[]{
#define OPCODE(name_token, type_token, ...) \
{ \
.name{#name_token}, \

6
src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp
View File

@ -263,7 +263,8 @@ private:
template <typename Type>
IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
for (IR::Block* const imm_pred : block->ImmPredecessors()) {
const bool is_thread_bit = std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
const bool is_thread_bit =
std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
}
return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
@ -347,7 +348,8 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
case IR::Opcode::GetThreadBitScalarReg:
case IR::Opcode::GetScalarRegister: {
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
inst.ReplaceUsesWith(pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
inst.ReplaceUsesWith(
pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
break;
}
case IR::Opcode::GetVectorRegister: {