From ba0be91c73a940bccdaf13a880ce8a3f72f60599 Mon Sep 17 00:00:00 2001 From: georgemoralis Date: Mon, 15 Jul 2024 14:18:28 +0300 Subject: [PATCH] clang format fix --- src/core/libraries/kernel/event_flag/event_flag_obj.h | 2 +- src/shader_recompiler/ir/breadth_first_search.h | 4 ++-- src/shader_recompiler/ir/opcodes.h | 2 +- src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp | 6 ++++-- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/core/libraries/kernel/event_flag/event_flag_obj.h b/src/core/libraries/kernel/event_flag/event_flag_obj.h index 99ae1981..fe50be69 100644 --- a/src/core/libraries/kernel/event_flag/event_flag_obj.h +++ b/src/core/libraries/kernel/event_flag/event_flag_obj.h @@ -20,7 +20,7 @@ public: EventFlagInternal(const std::string& name, ThreadMode thread_mode, QueueMode queue_mode, uint64_t bits) - : m_name(name), m_thread_mode(thread_mode), m_queue_mode(queue_mode), m_bits(bits) {}; + : m_name(name), m_thread_mode(thread_mode), m_queue_mode(queue_mode), m_bits(bits){}; int Wait(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result, u32* ptr_micros); int Poll(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result); diff --git a/src/shader_recompiler/ir/breadth_first_search.h b/src/shader_recompiler/ir/breadth_first_search.h index be46b48c..21a34a90 100644 --- a/src/shader_recompiler/ir/breadth_first_search.h +++ b/src/shader_recompiler/ir/breadth_first_search.h @@ -12,8 +12,8 @@ namespace Shader::IR { template -auto BreadthFirstSearch(const Value& value, - Pred&& pred) -> std::invoke_result_t { +auto BreadthFirstSearch(const Value& value, Pred&& pred) + -> std::invoke_result_t { if (value.IsImmediate()) { // Nothing to do with immediates return std::nullopt; diff --git a/src/shader_recompiler/ir/opcodes.h b/src/shader_recompiler/ir/opcodes.h index 22cc8c2b..66b60221 100644 --- a/src/shader_recompiler/ir/opcodes.h +++ b/src/shader_recompiler/ir/opcodes.h @@ -52,7 +52,7 @@ constexpr Type F64x2{Type::F64x2}; constexpr Type F64x3{Type::F64x3}; constexpr Type F64x4{Type::F64x4}; -constexpr OpcodeMeta META_TABLE[] { +constexpr OpcodeMeta META_TABLE[]{ #define OPCODE(name_token, type_token, ...) \ { \ .name{#name_token}, \ diff --git a/src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp b/src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp index 4699f09a..6a43ad6b 100644 --- a/src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp +++ b/src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp @@ -263,7 +263,8 @@ private: template IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) { for (IR::Block* const imm_pred : block->ImmPredecessors()) { - const bool is_thread_bit = std::is_same_v && phi.Flags() == IR::Type::U1; + const bool is_thread_bit = + std::is_same_v && phi.Flags() == IR::Type::U1; phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit)); } return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable)); @@ -347,7 +348,8 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) { case IR::Opcode::GetThreadBitScalarReg: case IR::Opcode::GetScalarRegister: { const IR::ScalarReg reg{inst.Arg(0).ScalarReg()}; - inst.ReplaceUsesWith(pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg)); + inst.ReplaceUsesWith( + pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg)); break; } case IR::Opcode::GetVectorRegister: {