clang format fix
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58d1cbd9b7
commit
ba0be91c73
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@ -20,7 +20,7 @@ public:
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EventFlagInternal(const std::string& name, ThreadMode thread_mode, QueueMode queue_mode,
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EventFlagInternal(const std::string& name, ThreadMode thread_mode, QueueMode queue_mode,
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uint64_t bits)
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uint64_t bits)
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: m_name(name), m_thread_mode(thread_mode), m_queue_mode(queue_mode), m_bits(bits) {};
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: m_name(name), m_thread_mode(thread_mode), m_queue_mode(queue_mode), m_bits(bits){};
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int Wait(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result, u32* ptr_micros);
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int Wait(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result, u32* ptr_micros);
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int Poll(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result);
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int Poll(u64 bits, WaitMode wait_mode, ClearMode clear_mode, u64* result);
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@ -12,8 +12,8 @@
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namespace Shader::IR {
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namespace Shader::IR {
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template <typename Pred>
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template <typename Pred>
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auto BreadthFirstSearch(const Value& value,
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auto BreadthFirstSearch(const Value& value, Pred&& pred)
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Pred&& pred) -> std::invoke_result_t<Pred, const Inst*> {
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-> std::invoke_result_t<Pred, const Inst*> {
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if (value.IsImmediate()) {
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if (value.IsImmediate()) {
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// Nothing to do with immediates
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// Nothing to do with immediates
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return std::nullopt;
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return std::nullopt;
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@ -52,7 +52,7 @@ constexpr Type F64x2{Type::F64x2};
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constexpr Type F64x3{Type::F64x3};
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constexpr Type F64x3{Type::F64x3};
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constexpr Type F64x4{Type::F64x4};
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constexpr Type F64x4{Type::F64x4};
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constexpr OpcodeMeta META_TABLE[] {
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constexpr OpcodeMeta META_TABLE[]{
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#define OPCODE(name_token, type_token, ...) \
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#define OPCODE(name_token, type_token, ...) \
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{ \
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{ \
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.name{#name_token}, \
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.name{#name_token}, \
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@ -263,7 +263,8 @@ private:
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template <typename Type>
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template <typename Type>
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IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
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IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
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for (IR::Block* const imm_pred : block->ImmPredecessors()) {
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for (IR::Block* const imm_pred : block->ImmPredecessors()) {
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const bool is_thread_bit = std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
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const bool is_thread_bit =
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std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
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phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
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phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
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}
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}
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return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
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return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
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@ -347,7 +348,8 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
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case IR::Opcode::GetThreadBitScalarReg:
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case IR::Opcode::GetThreadBitScalarReg:
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case IR::Opcode::GetScalarRegister: {
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case IR::Opcode::GetScalarRegister: {
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const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
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const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
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inst.ReplaceUsesWith(pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
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inst.ReplaceUsesWith(
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pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
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break;
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break;
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}
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}
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case IR::Opcode::GetVectorRegister: {
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case IR::Opcode::GetVectorRegister: {
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