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clang format fix

This commit is contained in:
georgemoralis 2024-07-15 14:18:28 +03:00
parent 58d1cbd9b7
commit ba0be91c73
4 changed files with 8 additions and 6 deletions
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4
src/shader_recompiler/ir/breadth_first_search.h
View File

@ -12,8 +12,8 @@
namespace Shader::IR { namespace Shader::IR {
template <typename Pred> template <typename Pred>
auto BreadthFirstSearch(const Value& value, auto BreadthFirstSearch(const Value& value, Pred&& pred)
Pred&& pred) -> std::invoke_result_t<Pred, const Inst*> { -> std::invoke_result_t<Pred, const Inst*> {
if (value.IsImmediate()) { if (value.IsImmediate()) {
// Nothing to do with immediates // Nothing to do with immediates
return std::nullopt; return std::nullopt;

6
src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp
View File

@ -263,7 +263,8 @@ private:
template <typename Type> template <typename Type>
IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) { IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
for (IR::Block* const imm_pred : block->ImmPredecessors()) { for (IR::Block* const imm_pred : block->ImmPredecessors()) {
const bool is_thread_bit = std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1; const bool is_thread_bit =
std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit)); phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
} }
return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable)); return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
@ -347,7 +348,8 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
case IR::Opcode::GetThreadBitScalarReg: case IR::Opcode::GetThreadBitScalarReg:
case IR::Opcode::GetScalarRegister: { case IR::Opcode::GetScalarRegister: {
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()}; const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
inst.ReplaceUsesWith(pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg)); inst.ReplaceUsesWith(
pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
break; break;
} }
case IR::Opcode::GetVectorRegister: { case IR::Opcode::GetVectorRegister: {