catto
/
shadPS4
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

add V_MAD_U32_U24 (#262) 

* V_MAD_U32_U24

* adjust V_MAD_I32_I24 for bit extraction

* optional bit extraction parameter

* Update vector_alu.cpp

* clang-format

* Update src/shader_recompiler/frontend/translate/vector_alu.cpp

Co-authored-by: TheTurtle <47210458+raphaelthegreat@users.noreply.github.com>

* Update vector_alu.cpp

* Update translate.h

---------

Co-authored-by: TheTurtle <47210458+raphaelthegreat@users.noreply.github.com>
This commit is contained in:
DanielSvoboda 2024-07-08 19:35:01 -03:00 committed by GitHub
parent ab6a1fb5f0
commit 63b0465a33
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/shader_recompiler/frontend/translate/translate.h
View File

@ -133,7 +133,7 @@ public:
void V_MUL_HI_U32(bool is_signed, const GcnInst& inst);
void V_SAD_U32(const GcnInst& inst);
void V_BFE_U32(bool is_signed, const GcnInst& inst);
void V_MAD_I32_I24(const GcnInst& inst);
void V_MAD_I32_I24(const GcnInst& inst, bool is_signed = true);
void V_MUL_I32_I24(const GcnInst& inst);
void V_SUB_I32(const GcnInst& inst);
void V_LSHR_B32(const GcnInst& inst);

11
src/shader_recompiler/frontend/translate/vector_alu.cpp
View File

@ -361,9 +361,11 @@ void Translator::V_BFE_U32(bool is_signed, const GcnInst& inst) {
SetDst(inst.dst[0], ir.BitFieldExtract(src0, src1, src2, is_signed));
}
void Translator::V_MAD_I32_I24(const GcnInst& inst) {
const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), true)};
const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), true)};
void Translator::V_MAD_I32_I24(const GcnInst& inst, bool is_signed) {
const IR::U32 src0{
ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), is_signed)};
const IR::U32 src1{
ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), is_signed)};
const IR::U32 src2{GetSrc(inst.src[2])};
SetDst(inst.dst[0], ir.IAdd(ir.IMul(src0, src1), src2));
}
@ -393,8 +395,7 @@ void Translator::V_ASHRREV_I32(const GcnInst& inst) {
}
void Translator::V_MAD_U32_U24(const GcnInst& inst) {
// TODO:
V_MAD_I32_I24(inst);
V_MAD_I32_I24(inst, false);
}
void Translator::V_RNDNE_F32(const GcnInst& inst) {