From 63b0465a335adef96383bba1c9b0102f38e625ba Mon Sep 17 00:00:00 2001 From: DanielSvoboda Date: Mon, 8 Jul 2024 19:35:01 -0300 Subject: [PATCH] add V_MAD_U32_U24 (#262) * V_MAD_U32_U24 * adjust V_MAD_I32_I24 for bit extraction * optional bit extraction parameter * Update vector_alu.cpp * clang-format * Update src/shader_recompiler/frontend/translate/vector_alu.cpp Co-authored-by: TheTurtle <47210458+raphaelthegreat@users.noreply.github.com> * Update vector_alu.cpp * Update translate.h --------- Co-authored-by: TheTurtle <47210458+raphaelthegreat@users.noreply.github.com> --- src/shader_recompiler/frontend/translate/translate.h | 2 +- .../frontend/translate/vector_alu.cpp | 11 ++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h index f8ea773b..5232b215 100644 --- a/src/shader_recompiler/frontend/translate/translate.h +++ b/src/shader_recompiler/frontend/translate/translate.h @@ -133,7 +133,7 @@ public: void V_MUL_HI_U32(bool is_signed, const GcnInst& inst); void V_SAD_U32(const GcnInst& inst); void V_BFE_U32(bool is_signed, const GcnInst& inst); - void V_MAD_I32_I24(const GcnInst& inst); + void V_MAD_I32_I24(const GcnInst& inst, bool is_signed = true); void V_MUL_I32_I24(const GcnInst& inst); void V_SUB_I32(const GcnInst& inst); void V_LSHR_B32(const GcnInst& inst); diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index 7bf24346..2b0367d6 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -361,9 +361,11 @@ void Translator::V_BFE_U32(bool is_signed, const GcnInst& inst) { SetDst(inst.dst[0], ir.BitFieldExtract(src0, src1, src2, is_signed)); } -void Translator::V_MAD_I32_I24(const GcnInst& inst) { - const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), true)}; - const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), true)}; +void Translator::V_MAD_I32_I24(const GcnInst& inst, bool is_signed) { + const IR::U32 src0{ + ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(24), is_signed)}; + const IR::U32 src1{ + ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(24), is_signed)}; const IR::U32 src2{GetSrc(inst.src[2])}; SetDst(inst.dst[0], ir.IAdd(ir.IMul(src0, src1), src2)); } @@ -393,8 +395,7 @@ void Translator::V_ASHRREV_I32(const GcnInst& inst) { } void Translator::V_MAD_U32_U24(const GcnInst& inst) { - // TODO: - V_MAD_I32_I24(inst); + V_MAD_I32_I24(inst, false); } void Translator::V_RNDNE_F32(const GcnInst& inst) {