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fix conflicts

This commit is contained in:
segf4ult 2024-08-27 12:00:21 +02:00
parent 64bacb20ce
commit b0d300b153
3 changed files with 19 additions and 8 deletions
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11
src/shader_recompiler/frontend/translate/vector_alu.cpp
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@ -396,12 +396,23 @@ void Translator::V_LSHL_B32(const GcnInst& inst) {
void Translator::V_LSHL_B64(const GcnInst& inst) { void Translator::V_LSHL_B64(const GcnInst& inst) {
const IR::U64 src0{GetSrc64(inst.src[0])}; const IR::U64 src0{GetSrc64(inst.src[0])};
<<<<<<< HEAD
const IR::U64 src1{GetSrc64(inst.src[1])}; const IR::U64 src1{GetSrc64(inst.src[1])};
const IR::VectorReg dst_reg{inst.dst[0].code}; const IR::VectorReg dst_reg{inst.dst[0].code};
ASSERT_MSG(src0.IsImmediate() && src0.U64() == 0 && src1.IsImmediate() && src1.U64() == 0, ASSERT_MSG(src0.IsImmediate() && src0.U64() == 0 && src1.IsImmediate() && src1.U64() == 0,
"V_LSHL_B64 with non-zero src0 or src1 is not supported"); "V_LSHL_B64 with non-zero src0 or src1 is not supported");
ir.SetVectorReg(dst_reg, ir.Imm32(0)); ir.SetVectorReg(dst_reg, ir.Imm32(0));
ir.SetVectorReg(dst_reg + 1, ir.Imm32(0)); ir.SetVectorReg(dst_reg + 1, ir.Imm32(0));
=======
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst64(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x3F))));
}
void Translator::V_LSHR_B64(const GcnInst& inst) {
const IR::U64 src0{GetSrc64(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst64(inst.dst[0], ir.ShiftRightLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x3F))));
>>>>>>> d5af6c3 (clang-format)
} }
void Translator::V_ADD_I32(const GcnInst& inst) { void Translator::V_ADD_I32(const GcnInst& inst) {

8
src/shader_recompiler/ir/ir_emitter.cpp
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@ -1119,13 +1119,13 @@ U32U64 IREmitter::BitwiseAnd(const U32U64& a, const U32U64& b) {
if (a.Type() != b.Type()) { if (a.Type() != b.Type()) {
UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type()); UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
} }
switch(a.Type()) { switch (a.Type()) {
case Type::U32: case Type::U32:
return Inst<U32>(Opcode::BitwiseAnd32, a, b); return Inst<U32>(Opcode::BitwiseAnd32, a, b);
case Type::U64: case Type::U64:
return Inst<U64>(Opcode::BitwiseAnd64, a, b); return Inst<U64>(Opcode::BitwiseAnd64, a, b);
default: default:
ThrowInvalidType(a.Type()); ThrowInvalidType(a.Type());
} }
} }

8
src/shader_recompiler/ir/passes/constant_propagation_pass.cpp
View File

@ -353,14 +353,14 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a & b; }); FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a & b; });
return; return;
case IR::Opcode::BitwiseAnd64: case IR::Opcode::BitwiseAnd64:
FoldWhenAllImmediates(inst, [](u64 a, u64 b) { return a & b; }); FoldWhenAllImmediates(inst, [](u64 a, u64 b) { return a & b; });
return; return;
case IR::Opcode::BitwiseOr32: case IR::Opcode::BitwiseOr32:
FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a | b; }); FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a | b; });
return; return;
case IR::Opcode::BitwiseOr64: case IR::Opcode::BitwiseOr64:
FoldWhenAllImmediates(inst, [](u64 a, u64 b) { return a | b; }); FoldWhenAllImmediates(inst, [](u64 a, u64 b) { return a | b; });
return; return;
case IR::Opcode::BitwiseXor32: case IR::Opcode::BitwiseXor32:
FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a ^ b; }); FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a ^ b; });
return; return;