Implement V_BFM_B32
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@ -189,6 +189,7 @@ public:
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void V_CMP_CLASS_F32(const GcnInst& inst);
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void V_CMP_CLASS_F32(const GcnInst& inst);
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void V_FFBL_B32(const GcnInst& inst);
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void V_FFBL_B32(const GcnInst& inst);
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void V_MBCNT_U32_B32(bool is_low, const GcnInst& inst);
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void V_MBCNT_U32_B32(bool is_low, const GcnInst& inst);
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void V_BFM_B32(const GcnInst& inst);
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// Vector Memory
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// Vector Memory
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void BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst);
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void BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst);
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@ -311,6 +311,9 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return V_MBCNT_U32_B32(false, inst);
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return V_MBCNT_U32_B32(false, inst);
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case Opcode::V_NOP:
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case Opcode::V_NOP:
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return;
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return;
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case Opcode::V_BFM_B32:
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return V_BFM_B32(inst);
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default:
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default:
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LogMissingOpcode(inst);
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LogMissingOpcode(inst);
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}
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}
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@ -964,4 +967,13 @@ void Translator::V_MBCNT_U32_B32(bool is_low, const GcnInst& inst) {
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SetDst(inst.dst[0], ir.LaneId());
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SetDst(inst.dst[0], ir.LaneId());
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}
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}
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void Translator::V_BFM_B32(const GcnInst& inst) {
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// bitmask width
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const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(4))};
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// bitmask offset
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const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(4))};
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const IR::U32 ones = ir.ISub(ir.ShiftLeftLogical(ir.Imm32(1), src0), ir.Imm32(1));
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SetDst(inst.dst[0], ir.ShiftLeftLogical(ones, src1));
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}
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} // namespace Shader::Gcn
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} // namespace Shader::Gcn
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