Patch `insertq`
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offtkp
parent
e57d55e6e9
commit
8e19ccd507
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@ -40,6 +40,15 @@ static Xbyak::Reg ZydisToXbyakRegisterOperand(const ZydisDecodedOperand& operand
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return ZydisToXbyakRegister(operand.reg.value);
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}
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static Xbyak::Xmm ZydisToXbyakVectorOperand(const ZydisDecodedOperand& operand) {
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const ZydisRegister reg = operand.reg.value;
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if (reg >= ZYDIS_REGISTER_XMM0 && reg <= ZYDIS_REGISTER_XMM15) {
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return Xbyak::Xmm(reg - ZYDIS_REGISTER_XMM0);
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}
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UNREACHABLE_MSG("Unsupported vector register: {}", static_cast<u32>(reg));
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}
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static Xbyak::Address ZydisToXbyakMemoryOperand(const ZydisDecodedOperand& operand) {
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ASSERT_MSG(operand.type == ZYDIS_OPERAND_TYPE_MEMORY, "Expected memory operand, got type: {}",
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static_cast<u32>(operand.type));
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@ -108,9 +117,7 @@ static Xbyak::Reg AllocateScratchRegister(
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UNREACHABLE_MSG("Out of scratch registers!");
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}
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#ifdef __APPLE__
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static constexpr u32 MaxSavedRegisters = 3;
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static constexpr u32 MaxSavedRegisters = 4;
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static pthread_key_t register_save_slots[MaxSavedRegisters];
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static std::once_flag register_save_init_flag;
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@ -155,6 +162,8 @@ static void RestoreRegisters(Xbyak::CodeGenerator& c,
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}
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}
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#ifdef __APPLE__
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static void GenerateANDN(const ZydisDecodedOperand* operands, Xbyak::CodeGenerator& c) {
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const auto dst = ZydisToXbyakRegisterOperand(operands[0]);
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const auto src1 = ZydisToXbyakRegisterOperand(operands[1]);
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@ -280,6 +289,11 @@ static bool FilterTcbAccess(const ZydisDecodedOperand* operands) {
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dst_op.reg.value <= ZYDIS_REGISTER_R15;
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}
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// For instructions that always need to be patched
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static bool FilterAlwaysTrue(const ZydisDecodedOperand*) {
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return true;
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}
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static void GenerateTcbAccess(const ZydisDecodedOperand* operands, Xbyak::CodeGenerator& c) {
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const auto dst = ZydisToXbyakRegisterOperand(operands[0]);
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const auto slot = GetTcbKey();
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@ -317,6 +331,133 @@ static void GenerateTcbAccess(const ZydisDecodedOperand* operands, Xbyak::CodeGe
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#endif
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}
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static void GenerateINSERTQ(const ZydisDecodedOperand* operands, Xbyak::CodeGenerator& c) {
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// INSERTQ Instruction Reference
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// Inserts bits from the lower 64 bits of the source operand into the lower 64 bits of the destination operand
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// No other bits in the lower 64 bits of the destination are modified. The upper 64 bits of the destination are undefined.
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// There's two forms of the instruction:
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// INSERTQ xmm1, xmm2, imm8, imm8
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// INSERTQ xmm1, xmm2
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// For the immediate form:
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// Insert field starting at bit 0 of xmm2 with the length
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// specified by [5:0] of the first immediate byte. This
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// field is inserted into xmm1 starting at the bit position
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// specified by [5:0] of the second immediate byte.
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// For the register form:
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// Insert field starting at bit 0 of xmm2 with the length
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// specified by xmm2[69:64]. This field is inserted into
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// xmm1 starting at the bit position specified by
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// xmm2[77:72].
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// A value of zero in the field length is defined as a length of 64. If the length field is 0 and the bit index
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// is 0, bits 63:0 of the source operand are inserted. For any other value of the bit index, the results are
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// undefined.
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bool immediateForm = operands[2].type == ZYDIS_OPERAND_TYPE_IMMEDIATE &&
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operands[3].type == ZYDIS_OPERAND_TYPE_IMMEDIATE;
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if (operands[0].type != ZYDIS_OPERAND_TYPE_REGISTER || operands[1].type != ZYDIS_OPERAND_TYPE_REGISTER) {
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ASSERT_MSG("operands 0 and 1 must be registers.");
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}
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const Xbyak::Xmm dst = ZydisToXbyakVectorOperand(operands[0]);
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const Xbyak::Xmm src = ZydisToXbyakVectorOperand(operands[1]);
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if (immediateForm) {
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u8 length = operands[2].imm.value.u & 0x3F;
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u8 index = operands[3].imm.value.u & 0x3F;
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if (length == 0) {
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length = 64;
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}
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if (length + index > 64) {
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ASSERT_MSG("length + index must be less than or equal to 64.");
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}
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const Xbyak::Reg64 scratch1 = AllocateScratchRegister({}, 64).cvt64();
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const Xbyak::Reg64 scratch2 = AllocateScratchRegister({&scratch1}, 64).cvt64();
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const Xbyak::Reg64 mask = AllocateScratchRegister({&scratch1, &scratch2}, 64).cvt64();
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u64 maskValue = (1ULL << length) - 1;
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SaveRegisters(c, {scratch1, scratch2, mask});
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c.movq(scratch1, src);
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c.movq(scratch2, dst);
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c.mov(mask, maskValue);
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// src &= mask
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c.and_(scratch1, mask);
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// src <<= index
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c.shl(scratch1, index);
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// dst &= ~(mask << index)
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maskValue = ~(maskValue << index);
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c.mov(mask, maskValue);
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c.and_(scratch2, mask);
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// dst |= src
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c.or_(scratch2, scratch1);
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// Insert scratch2 into low 64 bits of dst, upper 64 bits are unaffected
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c.pinsrq(dst, scratch2, 0);
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RestoreRegisters(c, {scratch1, scratch2, mask});
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} else {
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if (operands[2].type != ZYDIS_OPERAND_TYPE_UNUSED || operands[3].type != ZYDIS_OPERAND_TYPE_UNUSED) {
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ASSERT_MSG("operands 2 and 3 must be unused for register form.");
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}
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const Xbyak::Reg64 scratch1 = AllocateScratchRegister({}, 64).cvt64();
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const Xbyak::Reg64 scratch2 = AllocateScratchRegister({&scratch1}, 64).cvt64();
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const Xbyak::Reg64 index = AllocateScratchRegister({&scratch1, &scratch2}, 64).cvt64();
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const Xbyak::Reg64 mask = AllocateScratchRegister({&scratch1, &scratch2, &index}, 64).cvt64();
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SaveRegisters(c, {scratch1, scratch2, index, mask});
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// Get upper 64 bits of src
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c.pextrq(index, src, 1);
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c.mov(mask, index);
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c.mov(scratch1, 64); // for the cmovz below
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c.and_(mask, 0x3F); // mask now holds the length
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c.cmovz(mask, scratch1); // Check if length is 0, if so, set to 64
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// Get index to insert at
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c.shr(index, 8);
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c.and_(index, 0x3F);
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// Create a mask out of the length
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c.mov(scratch1, 1);
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c.shlx(mask, scratch1, mask);
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c.sub(mask, 1);
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c.movq(scratch1, src);
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c.movq(scratch2, dst);
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// src &= mask
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c.and_(scratch1, mask);
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// dst &= ~(mask << index)
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c.shlx(mask, mask, index);
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c.not_(mask);
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c.and_(scratch2, mask);
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// dst |= (src << index)
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c.shlx(scratch1, scratch1, index);
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c.or_(scratch2, scratch1);
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// Insert scratch2 into low 64 bits of dst, upper 64 bits are unaffected
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c.pinsrq(dst, scratch2, 0);
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RestoreRegisters(c, {scratch1, scratch2, index, mask});
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}
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}
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using PatchFilter = bool (*)(const ZydisDecodedOperand*);
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using InstructionGenerator = void (*)(const ZydisDecodedOperand*, Xbyak::CodeGenerator&);
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struct PatchInfo {
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@ -338,6 +479,8 @@ static const std::unordered_map<ZydisMnemonic, PatchInfo> Patches = {
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{ZYDIS_MNEMONIC_MOV, {FilterTcbAccess, GenerateTcbAccess, false}},
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#endif
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{ZYDIS_MNEMONIC_INSERTQ, {FilterAlwaysTrue, GenerateINSERTQ, true}},
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#ifdef __APPLE__
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// BMI1 instructions that are not supported by Rosetta 2 on Apple Silicon.
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{ZYDIS_MNEMONIC_ANDN, {FilterRosetta2Only, GenerateANDN, true}},
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