From 93ab48432e65369e4abe65865ed02febe01f350b Mon Sep 17 00:00:00 2001
From: Frodo Baggins <baggins31084@proton.me>
Date: Fri, 30 Aug 2024 01:06:08 -0700
Subject: [PATCH 1/3] Implement V_BFM_B32

---
 src/shader_recompiler/frontend/translate/translate.h |  1 +
 .../frontend/translate/vector_alu.cpp                | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h
index 8d418421..4522231e 100644
--- a/src/shader_recompiler/frontend/translate/translate.h
+++ b/src/shader_recompiler/frontend/translate/translate.h
@@ -189,6 +189,7 @@ public:
     void V_CMP_CLASS_F32(const GcnInst& inst);
     void V_FFBL_B32(const GcnInst& inst);
     void V_MBCNT_U32_B32(bool is_low, const GcnInst& inst);
+    void V_BFM_B32(const GcnInst& inst);
 
     // Vector Memory
     void BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst);
diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp
index 13a8342d..36fab906 100644
--- a/src/shader_recompiler/frontend/translate/vector_alu.cpp
+++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp
@@ -311,6 +311,9 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
         return V_MBCNT_U32_B32(false, inst);
     case Opcode::V_NOP:
         return;
+
+    case Opcode::V_BFM_B32:
+        return V_BFM_B32(inst);
     default:
         LogMissingOpcode(inst);
     }
@@ -964,4 +967,13 @@ void Translator::V_MBCNT_U32_B32(bool is_low, const GcnInst& inst) {
     SetDst(inst.dst[0], ir.LaneId());
 }
 
+void Translator::V_BFM_B32(const GcnInst& inst) {
+    // bitmask width
+    const IR::U32 src0{ir.BitFieldExtract(GetSrc(inst.src[0]), ir.Imm32(0), ir.Imm32(4))};
+    // bitmask offset
+    const IR::U32 src1{ir.BitFieldExtract(GetSrc(inst.src[1]), ir.Imm32(0), ir.Imm32(4))};
+    const IR::U32 ones = ir.ISub(ir.ShiftLeftLogical(ir.Imm32(1), src0), ir.Imm32(1));
+    SetDst(inst.dst[0], ir.ShiftLeftLogical(ones, src1));
+}
+
 } // namespace Shader::Gcn

From 70d6b7237708d18bbb117bdea4b28c5c249911e5 Mon Sep 17 00:00:00 2001
From: Frodo Baggins <baggins31084@proton.me>
Date: Fri, 30 Aug 2024 10:00:12 -0700
Subject: [PATCH 2/3] Render.Recompiler: Implement V_FFBH_U32

---
 src/shader_recompiler/frontend/translate/translate.h |  1 +
 .../frontend/translate/vector_alu.cpp                | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/src/shader_recompiler/frontend/translate/translate.h b/src/shader_recompiler/frontend/translate/translate.h
index 4522231e..f1619e81 100644
--- a/src/shader_recompiler/frontend/translate/translate.h
+++ b/src/shader_recompiler/frontend/translate/translate.h
@@ -190,6 +190,7 @@ public:
     void V_FFBL_B32(const GcnInst& inst);
     void V_MBCNT_U32_B32(bool is_low, const GcnInst& inst);
     void V_BFM_B32(const GcnInst& inst);
+    void V_FFBH_U32(const GcnInst& inst);
 
     // Vector Memory
     void BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst);
diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp
index 36fab906..e658456b 100644
--- a/src/shader_recompiler/frontend/translate/vector_alu.cpp
+++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp
@@ -314,6 +314,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
 
     case Opcode::V_BFM_B32:
         return V_BFM_B32(inst);
+    case Opcode::V_FFBH_U32:
+        return V_FFBH_U32(inst);
     default:
         LogMissingOpcode(inst);
     }
@@ -976,4 +978,14 @@ void Translator::V_BFM_B32(const GcnInst& inst) {
     SetDst(inst.dst[0], ir.ShiftLeftLogical(ones, src1));
 }
 
+void Translator::V_FFBH_U32(const GcnInst& inst) {
+    const IR::U32 src0{GetSrc(inst.src[0])};
+    // Gcn wants the MSB position counting from the left, but SPIR-V counts from the rightmost (LSB) position
+    const IR::U32 msb_pos = ir.FindUMsb(src0);
+    const IR::U32 pos_from_left = ir.ISub(ir.Imm32(31), msb_pos);
+    // Select 0xFFFFFFFF if src0 was 0
+    const IR::U1 cond = ir.INotEqual(src0, ir.Imm32(0));
+    SetDst(inst.dst[0], IR::U32{ir.Select(cond, pos_from_left, ir.Imm32(~0U))});
+}
+
 } // namespace Shader::Gcn

From c2f754196793fc6ad47334c70f4ef5b47011ab42 Mon Sep 17 00:00:00 2001
From: Frodo Baggins <baggins31084@proton.me>
Date: Fri, 30 Aug 2024 15:07:36 -0700
Subject: [PATCH 3/3] fix clang-format

---
 src/shader_recompiler/frontend/translate/vector_alu.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp
index e658456b..7fef9137 100644
--- a/src/shader_recompiler/frontend/translate/vector_alu.cpp
+++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp
@@ -980,7 +980,8 @@ void Translator::V_BFM_B32(const GcnInst& inst) {
 
 void Translator::V_FFBH_U32(const GcnInst& inst) {
     const IR::U32 src0{GetSrc(inst.src[0])};
-    // Gcn wants the MSB position counting from the left, but SPIR-V counts from the rightmost (LSB) position
+    // Gcn wants the MSB position counting from the left, but SPIR-V counts from the rightmost (LSB)
+    // position
     const IR::U32 msb_pos = ir.FindUMsb(src0);
     const IR::U32 pos_from_left = ir.ISub(ir.Imm32(31), msb_pos);
     // Select 0xFFFFFFFF if src0 was 0