Render.Recompiler: Implement V_FFBH_U32
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@ -190,6 +190,7 @@ public:
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void V_FFBL_B32(const GcnInst& inst);
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void V_FFBL_B32(const GcnInst& inst);
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void V_MBCNT_U32_B32(bool is_low, const GcnInst& inst);
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void V_MBCNT_U32_B32(bool is_low, const GcnInst& inst);
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void V_BFM_B32(const GcnInst& inst);
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void V_BFM_B32(const GcnInst& inst);
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void V_FFBH_U32(const GcnInst& inst);
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// Vector Memory
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// Vector Memory
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void BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst);
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void BUFFER_LOAD(u32 num_dwords, bool is_typed, const GcnInst& inst);
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@ -314,6 +314,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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case Opcode::V_BFM_B32:
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case Opcode::V_BFM_B32:
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return V_BFM_B32(inst);
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return V_BFM_B32(inst);
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case Opcode::V_FFBH_U32:
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return V_FFBH_U32(inst);
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default:
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default:
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LogMissingOpcode(inst);
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LogMissingOpcode(inst);
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}
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}
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@ -976,4 +978,14 @@ void Translator::V_BFM_B32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.ShiftLeftLogical(ones, src1));
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SetDst(inst.dst[0], ir.ShiftLeftLogical(ones, src1));
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}
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}
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void Translator::V_FFBH_U32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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// Gcn wants the MSB position counting from the left, but SPIR-V counts from the rightmost (LSB) position
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const IR::U32 msb_pos = ir.FindUMsb(src0);
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const IR::U32 pos_from_left = ir.ISub(ir.Imm32(31), msb_pos);
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// Select 0xFFFFFFFF if src0 was 0
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const IR::U1 cond = ir.INotEqual(src0, ir.Imm32(0));
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SetDst(inst.dst[0], IR::U32{ir.Select(cond, pos_from_left, ir.Imm32(~0U))});
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}
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} // namespace Shader::Gcn
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} // namespace Shader::Gcn
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