video_core: Minor fixes (#366)
* data_share: Fix DS instruction * vk_graphics_pipeline: Fix unnecessary invalidate * spirv: Remove subgroup id * vector_alu: Simplify mbcnt pattern * shader_recompiler: More instructions * clang format * kernel: Fix cond memory leak and reduce spam * liverpool: Print error on exception * build fix
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cdff4af38d
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159be2c7f4
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@ -727,6 +727,9 @@ int PS4_SYSV_ABI scePthreadCondDestroy(ScePthreadCond* cond) {
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LOG_INFO(Kernel_Pthread, "scePthreadCondDestroy, result={}", result);
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delete *cond;
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*cond = nullptr;
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switch (result) {
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case 0:
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return SCE_OK;
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@ -1142,7 +1145,7 @@ int PS4_SYSV_ABI scePthreadCondWait(ScePthreadCond* cond, ScePthreadMutex* mutex
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}
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int result = pthread_cond_wait(&(*cond)->cond, &(*mutex)->pth_mutex);
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LOG_INFO(Kernel_Pthread, "scePthreadCondWait, result={}", result);
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LOG_DEBUG(Kernel_Pthread, "scePthreadCondWait, result={}", result);
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switch (result) {
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case 0:
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@ -1162,7 +1165,7 @@ int PS4_SYSV_ABI scePthreadCondattrDestroy(ScePthreadCondattr* attr) {
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}
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int result = pthread_condattr_destroy(&(*attr)->cond_attr);
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LOG_INFO(Kernel_Pthread, "scePthreadCondattrDestroy: result = {} ", result);
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LOG_DEBUG(Kernel_Pthread, "scePthreadCondattrDestroy: result = {} ", result);
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switch (result) {
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case 0:
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@ -11,7 +11,7 @@ Id SubgroupScope(EmitContext& ctx) {
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}
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Id EmitWarpId(EmitContext& ctx) {
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return ctx.OpLoad(ctx.U32[1], ctx.subgroup_id);
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UNREACHABLE();
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}
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Id EmitLaneId(EmitContext& ctx) {
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@ -225,7 +225,6 @@ void EmitContext::DefineInputs(const Info& info) {
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break;
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}
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case Stage::Fragment:
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subgroup_id = DefineVariable(U32[1], spv::BuiltIn::SubgroupId, spv::StorageClass::Input);
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subgroup_local_invocation_id = DefineVariable(
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U32[1], spv::BuiltIn::SubgroupLocalInvocationId, spv::StorageClass::Input);
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Decorate(subgroup_local_invocation_id, spv::Decoration::Flat);
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@ -180,7 +180,6 @@ public:
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Id workgroup_id{};
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Id local_invocation_id{};
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Id subgroup_id{};
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Id subgroup_local_invocation_id{};
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Id image_u32{};
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@ -48,7 +48,8 @@ void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnIn
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IR::VectorReg dst_reg{inst.dst[0].code};
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if (is_pair) {
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// Pair loads are either 32 or 64-bit
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const u32 adj = bit_size == 32 ? 4 : 8;
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0 * adj)));
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const IR::Value data0 = ir.LoadShared(bit_size, is_signed, addr0);
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if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data0});
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@ -56,7 +57,7 @@ void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnIn
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data0, 0)});
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data0, 1)});
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}
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1 * adj)));
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const IR::Value data1 = ir.LoadShared(bit_size, is_signed, addr1);
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if (bit_size == 32) {
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ir.SetVectorReg(dst_reg++, IR::U32{data1});
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@ -65,11 +66,13 @@ void Translator::DS_READ(int bit_size, bool is_signed, bool is_pair, const GcnIn
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ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(data1, 1)});
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}
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} else if (bit_size == 64) {
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const IR::Value data = ir.LoadShared(bit_size, is_signed, addr);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::Value data = ir.LoadShared(bit_size, is_signed, addr0);
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ir.SetVectorReg(dst_reg, IR::U32{ir.CompositeExtract(data, 0)});
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ir.SetVectorReg(dst_reg + 1, IR::U32{ir.CompositeExtract(data, 1)});
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} else {
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const IR::U32 data = IR::U32{ir.LoadShared(bit_size, is_signed, addr)};
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::U32 data = IR::U32{ir.LoadShared(bit_size, is_signed, addr0)};
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ir.SetVectorReg(dst_reg, data);
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}
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}
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@ -79,7 +82,8 @@ void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnI
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const IR::VectorReg data0{inst.src[1].code};
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const IR::VectorReg data1{inst.src[2].code};
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if (is_pair) {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const u32 adj = bit_size == 32 ? 4 : 8;
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0 * adj)));
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if (bit_size == 32) {
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ir.WriteShared(32, ir.GetVectorReg(data0), addr0);
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} else {
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@ -87,7 +91,7 @@ void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnI
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64, ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1)),
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addr0);
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}
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1)));
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const IR::U32 addr1 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset1 * adj)));
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if (bit_size == 32) {
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ir.WriteShared(32, ir.GetVectorReg(data1), addr1);
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} else {
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@ -96,11 +100,13 @@ void Translator::DS_WRITE(int bit_size, bool is_signed, bool is_pair, const GcnI
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addr1);
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}
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} else if (bit_size == 64) {
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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const IR::Value data =
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ir.CompositeConstruct(ir.GetVectorReg(data0), ir.GetVectorReg(data0 + 1));
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ir.WriteShared(bit_size, data, addr);
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ir.WriteShared(bit_size, data, addr0);
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} else {
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ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr);
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const IR::U32 addr0 = ir.IAdd(addr, ir.Imm32(u32(inst.control.ds.offset0)));
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ir.WriteShared(bit_size, ir.GetVectorReg(data0), addr0);
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}
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}
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@ -125,6 +125,7 @@ public:
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void V_ADD_F32(const GcnInst& inst);
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void V_CVT_OFF_F32_I4(const GcnInst& inst);
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void V_MED3_F32(const GcnInst& inst);
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void V_MED3_I32(const GcnInst& inst);
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void V_FLOOR_F32(const GcnInst& inst);
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void V_SUB_F32(const GcnInst& inst);
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void V_RCP_F32(const GcnInst& inst);
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@ -159,6 +160,7 @@ public:
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void V_SUB_I32(const GcnInst& inst);
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void V_LSHR_B32(const GcnInst& inst);
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void V_ASHRREV_I32(const GcnInst& inst);
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void V_ASHR_I32(const GcnInst& inst);
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void V_MAD_U32_U24(const GcnInst& inst);
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void V_RNDNE_F32(const GcnInst& inst);
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void V_BCNT_U32_B32(const GcnInst& inst);
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@ -24,6 +24,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return V_LSHR_B32(inst);
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case Opcode::V_ASHRREV_I32:
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return V_ASHRREV_I32(inst);
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case Opcode::V_ASHR_I32:
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return V_ASHR_I32(inst);
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case Opcode::V_LSHRREV_B32:
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return V_LSHRREV_B32(inst);
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case Opcode::V_NOT_B32:
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@ -183,6 +185,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return V_ADD_F32(inst);
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case Opcode::V_MED3_F32:
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return V_MED3_F32(inst);
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case Opcode::V_MED3_I32:
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return V_MED3_I32(inst);
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case Opcode::V_FLOOR_F32:
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return V_FLOOR_F32(inst);
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case Opcode::V_SUB_F32:
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@ -479,6 +483,14 @@ void Translator::V_MED3_F32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.FPMax(ir.FPMin(src0, src1), mmx));
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}
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void Translator::V_MED3_I32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 src2{GetSrc(inst.src[2])};
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const IR::U32 mmx = ir.SMin(ir.SMax(src0, src1), src2);
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SetDst(inst.dst[0], ir.SMax(ir.SMin(src0, src1), mmx));
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}
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void Translator::V_FLOOR_F32(const GcnInst& inst) {
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const IR::F32 src0{GetSrc(inst.src[0], true)};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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@ -760,6 +772,12 @@ void Translator::V_ASHRREV_I32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.ShiftRightArithmetic(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
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}
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void Translator::V_ASHR_I32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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SetDst(inst.dst[0], ir.ShiftRightArithmetic(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
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}
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void Translator::V_MAD_U32_U24(const GcnInst& inst) {
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V_MAD_I32_I24(inst, false);
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}
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@ -925,25 +943,12 @@ void Translator::V_FFBL_B32(const GcnInst& inst) {
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void Translator::V_MBCNT_U32_B32(bool is_low, const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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const IR::U32 lane_id = ir.LaneId();
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const auto [warp_half, mask_shift] = [&]() -> std::pair<IR::U32, IR::U32> {
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if (profile.subgroup_size == 32) {
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const IR::U32 warp_half = ir.BitwiseAnd(ir.WarpId(), ir.Imm32(1));
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return std::make_pair(warp_half, lane_id);
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}
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const IR::U32 warp_half = ir.ShiftRightLogical(lane_id, ir.Imm32(5));
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const IR::U32 mask_shift = ir.BitwiseAnd(lane_id, ir.Imm32(0x1F));
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return std::make_pair(warp_half, mask_shift);
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}();
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const IR::U32 thread_mask = ir.ISub(ir.ShiftLeftLogical(ir.Imm32(1), mask_shift), ir.Imm32(1));
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const IR::U1 is_odd_warp = ir.INotEqual(warp_half, ir.Imm32(0));
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const IR::U32 mask = IR::U32{ir.Select(is_odd_warp, is_low ? ir.Imm32(~0U) : thread_mask,
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is_low ? thread_mask : ir.Imm32(0))};
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const IR::U32 masked_value = ir.BitwiseAnd(src0, mask);
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const IR::U32 result = ir.IAdd(src1, ir.BitCount(masked_value));
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SetDst(inst.dst[0], result);
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if (!is_low) {
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ASSERT(src0.IsImmediate() && src0.U32() == ~0U && src1.IsImmediate() && src1.U32() == 0U);
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return;
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}
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ASSERT(src0.IsImmediate() && src0.U32() == ~0U);
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SetDst(inst.dst[0], ir.LaneId());
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}
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} // namespace Shader::Gcn
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@ -6,7 +6,7 @@
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#include <array>
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#include <condition_variable>
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#include <coroutine>
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#include <functional>
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#include <exception>
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#include <mutex>
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#include <span>
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#include <thread>
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@ -1040,7 +1040,11 @@ private:
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return {};
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}
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void unhandled_exception() {
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UNREACHABLE();
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try {
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std::rethrow_exception(std::current_exception());
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} catch (const std::exception& e) {
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UNREACHABLE_MSG("Unhandled exception: {}", e.what());
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}
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}
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void return_void() {}
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struct empty {};
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@ -94,7 +94,9 @@ bool ComputePipeline::BindResources(Core::MemoryManager* memory, StreamBuffer& s
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const auto vsharp = buffer.GetVsharp(info);
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const u32 size = vsharp.GetSize();
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const VAddr address = vsharp.base_address;
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texture_cache.OnCpuWrite(address);
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if (buffer.is_storage) {
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texture_cache.OnCpuWrite(address);
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}
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const u32 offset = staging.Copy(address, size,
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buffer.is_storage ? instance.StorageMinAlignment()
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: instance.UniformMinAlignment());
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