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2 Commits
main ... fp3216

Author SHA1 Message Date
IndecisiveTurtle c869f0df0b temp: Comment out protect 2024-07-26 15:15:38 +03:00
IndecisiveTurtle a76828399c translator: Implemtn f32 to f16 convert 2024-07-26 14:04:15 +03:00
10 changed files with 30 additions and 5 deletions

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@ -84,6 +84,9 @@ static PS4_SYSV_ABI void stack_chk_fail() {
int PS4_SYSV_ABI sceKernelMunmap(void* addr, size_t len) { int PS4_SYSV_ABI sceKernelMunmap(void* addr, size_t len) {
LOG_INFO(Kernel_Vmm, "addr = {}, len = {:#x}", fmt::ptr(addr), len); LOG_INFO(Kernel_Vmm, "addr = {}, len = {:#x}", fmt::ptr(addr), len);
if (len == 0) {
return ORBIS_OK;
}
auto* memory = Core::Memory::Instance(); auto* memory = Core::Memory::Instance();
memory->UnmapMemory(std::bit_cast<VAddr>(addr), len); memory->UnmapMemory(std::bit_cast<VAddr>(addr), len);
return SCE_OK; return SCE_OK;

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@ -6,8 +6,8 @@
namespace Shader::Backend::SPIRV { namespace Shader::Backend::SPIRV {
void EmitBitCastU16F16(EmitContext&) { Id EmitBitCastU16F16(EmitContext& ctx, Id value) {
UNREACHABLE_MSG("SPIR-V Instruction"); return ctx.OpBitcast(ctx.U16, value);
} }
Id EmitBitCastU32F32(EmitContext& ctx, Id value) { Id EmitBitCastU32F32(EmitContext& ctx, Id value) {

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@ -259,4 +259,8 @@ Id EmitConvertU16U32(EmitContext& ctx, Id value) {
return ctx.OpUConvert(ctx.U16, value); return ctx.OpUConvert(ctx.U16, value);
} }
Id EmitConvertU32U16(EmitContext& ctx, Id value) {
return ctx.OpUConvert(ctx.U32[1], value);
}
} // namespace Shader::Backend::SPIRV } // namespace Shader::Backend::SPIRV

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@ -148,7 +148,7 @@ Id EmitSelectU64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value); Id EmitSelectF16(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value); Id EmitSelectF32(EmitContext& ctx, Id cond, Id true_value, Id false_value);
Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value); Id EmitSelectF64(EmitContext& ctx, Id cond, Id true_value, Id false_value);
void EmitBitCastU16F16(EmitContext& ctx); Id EmitBitCastU16F16(EmitContext& ctx, Id value);
Id EmitBitCastU32F32(EmitContext& ctx, Id value); Id EmitBitCastU32F32(EmitContext& ctx, Id value);
void EmitBitCastU64F64(EmitContext& ctx); void EmitBitCastU64F64(EmitContext& ctx);
Id EmitBitCastF16U16(EmitContext& ctx, Id value); Id EmitBitCastF16U16(EmitContext& ctx, Id value);
@ -349,6 +349,7 @@ Id EmitConvertF64U16(EmitContext& ctx, Id value);
Id EmitConvertF64U32(EmitContext& ctx, Id value); Id EmitConvertF64U32(EmitContext& ctx, Id value);
Id EmitConvertF64U64(EmitContext& ctx, Id value); Id EmitConvertF64U64(EmitContext& ctx, Id value);
Id EmitConvertU16U32(EmitContext& ctx, Id value); Id EmitConvertU16U32(EmitContext& ctx, Id value);
Id EmitConvertU32U16(EmitContext& ctx, Id value);
Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id bias_lc, Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id bias_lc,
Id offset); Id offset);

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@ -371,6 +371,9 @@ void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_l
case Opcode::V_CVT_F32_F16: case Opcode::V_CVT_F32_F16:
translator.V_CVT_F32_F16(inst); translator.V_CVT_F32_F16(inst);
break; break;
case Opcode::V_CVT_F16_F32:
translator.V_CVT_F16_F32(inst);
break;
case Opcode::V_CVT_F32_UBYTE0: case Opcode::V_CVT_F32_UBYTE0:
translator.V_CVT_F32_UBYTE(0, inst); translator.V_CVT_F32_UBYTE(0, inst);
break; break;

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@ -94,6 +94,7 @@ public:
void V_MAC_F32(const GcnInst& inst); void V_MAC_F32(const GcnInst& inst);
void V_CVT_PKRTZ_F16_F32(const GcnInst& inst); void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
void V_CVT_F32_F16(const GcnInst& inst); void V_CVT_F32_F16(const GcnInst& inst);
void V_CVT_F16_F32(const GcnInst& inst);
void V_MUL_F32(const GcnInst& inst); void V_MUL_F32(const GcnInst& inst);
void V_CNDMASK_B32(const GcnInst& inst); void V_CNDMASK_B32(const GcnInst& inst);
void V_OR_B32(bool is_xor, const GcnInst& inst); void V_OR_B32(bool is_xor, const GcnInst& inst);

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@ -32,6 +32,12 @@ void Translator::V_CVT_F32_F16(const GcnInst& inst) {
SetDst(inst.dst[0], ir.FPConvert(32, ir.BitCast<IR::F16>(src0l))); SetDst(inst.dst[0], ir.FPConvert(32, ir.BitCast<IR::F16>(src0l)));
} }
void Translator::V_CVT_F16_F32(const GcnInst& inst) {
const IR::F32 src0 = GetSrc(inst.src[0], true);
const IR::F16 src0fp16 = ir.FPConvert(16, src0);
SetDst(inst.dst[0], ir.UConvert(32, ir.BitCast<IR::U16>(src0fp16)));
}
void Translator::V_MUL_F32(const GcnInst& inst) { void Translator::V_MUL_F32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.FPMul(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true))); SetDst(inst.dst[0], ir.FPMul(GetSrc(inst.src[0], true), GetSrc(inst.src[1], true)));
} }

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@ -1228,7 +1228,13 @@ U16U32U64 IREmitter::UConvert(size_t result_bitsize, const U16U32U64& value) {
case Type::U32: case Type::U32:
return Inst<U16>(Opcode::ConvertU16U32, value); return Inst<U16>(Opcode::ConvertU16U32, value);
} }
case 32:
switch (value.Type()) {
case Type::U16:
return Inst<U32>(Opcode::ConvertU32U16, value);
} }
}
throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize); throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
} }

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@ -289,6 +289,7 @@ OPCODE(ConvertF64S32, F64, U32,
OPCODE(ConvertF64U32, F64, U32, ) OPCODE(ConvertF64U32, F64, U32, )
OPCODE(ConvertF32U16, F32, U16, ) OPCODE(ConvertF32U16, F32, U16, )
OPCODE(ConvertU16U32, U16, U32, ) OPCODE(ConvertU16U32, U16, U32, )
OPCODE(ConvertU32U16, U32, U16, )
// Image operations // Image operations
OPCODE(ImageSampleImplicitLod, F32x4, Opaque, Opaque, Opaque, Opaque, ) OPCODE(ImageSampleImplicitLod, F32x4, Opaque, Opaque, Opaque, Opaque, )

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@ -421,9 +421,9 @@ void TextureCache::UpdatePagesCachedCount(VAddr addr, u64 size, s32 delta) {
const u32 interval_size = interval_end_addr - interval_start_addr; const u32 interval_size = interval_end_addr - interval_start_addr;
void* addr = reinterpret_cast<void*>(interval_start_addr); void* addr = reinterpret_cast<void*>(interval_start_addr);
if (delta > 0 && count == delta) { if (delta > 0 && count == delta) {
mprotect(addr, interval_size, PAGE_READONLY); //mprotect(addr, interval_size, PAGE_READONLY);
} else if (delta < 0 && count == -delta) { } else if (delta < 0 && count == -delta) {
mprotect(addr, interval_size, PAGE_READWRITE); //mprotect(addr, interval_size, PAGE_READWRITE);
} else { } else {
ASSERT(count >= 0); ASSERT(count >= 0);
} }