spirv: Handle tgid enable bits

src/core/libraries/network/net.cpp

@@ -10,7 +10,6 @@
 #include <arpa/inet.h>
 #endif
 
-#include <thread>
 #include "common/assert.h"
 #include "common/logging/log.h"
 #include "core/libraries/error_codes.h"
@@ -60,7 +59,6 @@ int PS4_SYSV_ABI sce_net_in6addr_nodelocal_allnodes() {
 }
 
 OrbisNetId PS4_SYSV_ABI sceNetAccept(OrbisNetId s, OrbisNetSockaddr* addr, u32* paddrlen) {
-    std::this_thread::sleep_for(std::chrono::seconds(5));
     LOG_ERROR(Lib_Net, "(STUBBED) called");
     return ORBIS_OK;
 }

src/shader_recompiler/frontend/control_flow_graph.cpp

@@ -146,9 +146,6 @@ void CFG::EmitDivergenceLabels() {
 
     // Sort labels to make sure block insertion is correct.
     std::ranges::sort(labels);
-    for (const auto label : labels) {
-        LOG_INFO(Render_Vulkan, "Emitting label {:#x}", label);
-    }
 }
 
 void CFG::EmitBlocks() {
@@ -165,7 +162,7 @@ void CFG::EmitBlocks() {
         const Label end = *next_it;
         const size_t end_index = GetIndex(end) - 1;
         const auto& end_inst = inst_list[end_index];
-        LOG_INFO(Render_Vulkan, "Emitting block {:#x}-{:#x}", start, end);
+
         // Insert block between the labels using the last instruction
         // as an indicator for branching type.
         Block* block = block_pool.Create();

src/shader_recompiler/frontend/translate/translate.cpp

@@ -64,9 +64,15 @@ void Translator::EmitPrologue() {
         ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 1));
         ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 2));
 
-        ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
+        if (info.tgid_enable[0]) {
-        ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
+            ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
-        ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
+        }
+        if (info.tgid_enable[1]) {
+            ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
+        }
+        if (info.tgid_enable[2]) {
+            ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
+        }
         break;
     default:
         throw NotImplementedException("Unknown shader stage");

src/shader_recompiler/runtime_info.h

@@ -180,6 +180,7 @@ struct Info {
     SamplerResourceList samplers;
 
     std::array<u32, 3> workgroup_size{};
+    std::array<bool, 3> tgid_enable;
 
     u32 num_user_data;
     u32 num_input_vgprs;

src/video_core/amdgpu/liverpool.cpp

@@ -180,10 +180,6 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
             UNREACHABLE_MSG("Invalid PM4 type {}", type);
         }
 
-        if (VAddr(dcb.data()) == 0x3c24df50) {
-            printf("bad\n");
-        }
-
         const u32 count = header->type3.NumWords();
         const PM4ItOpcode opcode = header->type3.opcode;
         switch (opcode) {

src/video_core/amdgpu/liverpool.h

@@ -130,6 +130,7 @@ struct Liverpool {
             BitField<0, 6, u64> num_vgprs;
             BitField<6, 4, u64> num_sgprs;
             BitField<33, 5, u64> num_user_regs;
+            BitField<39, 3, u64> tgid_enable;
             BitField<47, 9, u64> lds_dwords;
         } settings;
         INSERT_PADDING_WORDS(1);
@@ -148,6 +149,10 @@ struct Liverpool {
             return settings.lds_dwords.Value() * 128 * 4;
         }
 
+        bool IsTgidEnabled(u32 i) const noexcept {
+            return (settings.tgid_enable.Value() >> i) & 1;
+        }
+
         std::span<const u32> Code() const {
             const u32* code = Address<u32*>();
             BinaryInfo bininfo;

src/video_core/buffer_cache/buffer_cache.cpp

@@ -1,6 +1,6 @@
 // SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
 // SPDX-License-Identifier: GPL-2.0-or-later
-#pragma clang optimize off
+
 #include <algorithm>
 #include "common/alignment.h"
 #include "common/scope_exit.h"

src/video_core/buffer_cache/buffer_cache.h

@@ -3,7 +3,6 @@
 
 #pragma once
 
-#include <array>
 #include <mutex>
 #include <boost/container/small_vector.hpp>
 #include <boost/icl/interval_map.hpp>

src/video_core/renderer_vulkan/vk_pipeline_cache.cpp

@@ -93,6 +93,8 @@ Shader::Info MakeShaderInfo(Shader::Stage stage, std::span<const u32, 16> user_d
         info.num_user_data = cs_pgm.settings.num_user_regs;
         info.workgroup_size = {cs_pgm.num_thread_x.full, cs_pgm.num_thread_y.full,
                                cs_pgm.num_thread_z.full};
+        info.tgid_enable = {cs_pgm.IsTgidEnabled(0), cs_pgm.IsTgidEnabled(1),
+                            cs_pgm.IsTgidEnabled(2)};
         info.shared_memory_size = cs_pgm.SharedMemSize();
         break;
     }