spirv: Handle tgid enable bits
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1ca8a5c3c9
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e47a61dec9
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@ -10,7 +10,6 @@
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#include <arpa/inet.h>
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#include <arpa/inet.h>
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#endif
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#endif
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#include <thread>
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#include "common/assert.h"
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/logging/log.h"
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#include "core/libraries/error_codes.h"
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#include "core/libraries/error_codes.h"
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@ -60,7 +59,6 @@ int PS4_SYSV_ABI sce_net_in6addr_nodelocal_allnodes() {
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}
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}
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OrbisNetId PS4_SYSV_ABI sceNetAccept(OrbisNetId s, OrbisNetSockaddr* addr, u32* paddrlen) {
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OrbisNetId PS4_SYSV_ABI sceNetAccept(OrbisNetId s, OrbisNetSockaddr* addr, u32* paddrlen) {
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std::this_thread::sleep_for(std::chrono::seconds(5));
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LOG_ERROR(Lib_Net, "(STUBBED) called");
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LOG_ERROR(Lib_Net, "(STUBBED) called");
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return ORBIS_OK;
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return ORBIS_OK;
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}
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}
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@ -146,9 +146,6 @@ void CFG::EmitDivergenceLabels() {
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// Sort labels to make sure block insertion is correct.
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// Sort labels to make sure block insertion is correct.
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std::ranges::sort(labels);
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std::ranges::sort(labels);
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for (const auto label : labels) {
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LOG_INFO(Render_Vulkan, "Emitting label {:#x}", label);
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}
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}
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}
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void CFG::EmitBlocks() {
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void CFG::EmitBlocks() {
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@ -165,7 +162,7 @@ void CFG::EmitBlocks() {
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const Label end = *next_it;
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const Label end = *next_it;
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const size_t end_index = GetIndex(end) - 1;
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const size_t end_index = GetIndex(end) - 1;
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const auto& end_inst = inst_list[end_index];
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const auto& end_inst = inst_list[end_index];
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LOG_INFO(Render_Vulkan, "Emitting block {:#x}-{:#x}", start, end);
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// Insert block between the labels using the last instruction
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// Insert block between the labels using the last instruction
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// as an indicator for branching type.
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// as an indicator for branching type.
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Block* block = block_pool.Create();
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Block* block = block_pool.Create();
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@ -64,9 +64,15 @@ void Translator::EmitPrologue() {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 1));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 1));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 2));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::LocalInvocationId, 2));
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if (info.tgid_enable[0]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 0));
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}
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if (info.tgid_enable[1]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 1));
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}
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if (info.tgid_enable[2]) {
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
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ir.SetScalarReg(dst_sreg++, ir.GetAttributeU32(IR::Attribute::WorkgroupId, 2));
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}
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break;
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break;
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default:
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default:
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throw NotImplementedException("Unknown shader stage");
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throw NotImplementedException("Unknown shader stage");
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@ -180,6 +180,7 @@ struct Info {
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SamplerResourceList samplers;
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SamplerResourceList samplers;
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std::array<u32, 3> workgroup_size{};
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std::array<u32, 3> workgroup_size{};
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std::array<bool, 3> tgid_enable;
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u32 num_user_data;
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u32 num_user_data;
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u32 num_input_vgprs;
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u32 num_input_vgprs;
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@ -180,10 +180,6 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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UNREACHABLE_MSG("Invalid PM4 type {}", type);
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UNREACHABLE_MSG("Invalid PM4 type {}", type);
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}
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}
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if (VAddr(dcb.data()) == 0x3c24df50) {
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printf("bad\n");
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}
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const u32 count = header->type3.NumWords();
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const u32 count = header->type3.NumWords();
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const PM4ItOpcode opcode = header->type3.opcode;
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const PM4ItOpcode opcode = header->type3.opcode;
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switch (opcode) {
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switch (opcode) {
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@ -130,6 +130,7 @@ struct Liverpool {
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BitField<0, 6, u64> num_vgprs;
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BitField<0, 6, u64> num_vgprs;
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BitField<6, 4, u64> num_sgprs;
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BitField<6, 4, u64> num_sgprs;
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BitField<33, 5, u64> num_user_regs;
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BitField<33, 5, u64> num_user_regs;
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BitField<39, 3, u64> tgid_enable;
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BitField<47, 9, u64> lds_dwords;
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BitField<47, 9, u64> lds_dwords;
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} settings;
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} settings;
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INSERT_PADDING_WORDS(1);
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INSERT_PADDING_WORDS(1);
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@ -148,6 +149,10 @@ struct Liverpool {
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return settings.lds_dwords.Value() * 128 * 4;
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return settings.lds_dwords.Value() * 128 * 4;
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}
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}
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bool IsTgidEnabled(u32 i) const noexcept {
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return (settings.tgid_enable.Value() >> i) & 1;
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}
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std::span<const u32> Code() const {
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std::span<const u32> Code() const {
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const u32* code = Address<u32*>();
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const u32* code = Address<u32*>();
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BinaryInfo bininfo;
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BinaryInfo bininfo;
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@ -1,6 +1,6 @@
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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// SPDX-License-Identifier: GPL-2.0-or-later
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#pragma clang optimize off
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#include <algorithm>
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#include <algorithm>
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#include "common/alignment.h"
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#include "common/alignment.h"
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#include "common/scope_exit.h"
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#include "common/scope_exit.h"
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@ -3,7 +3,6 @@
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#pragma once
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#pragma once
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#include <array>
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#include <mutex>
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#include <mutex>
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#include <boost/container/small_vector.hpp>
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#include <boost/container/small_vector.hpp>
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#include <boost/icl/interval_map.hpp>
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#include <boost/icl/interval_map.hpp>
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@ -93,6 +93,8 @@ Shader::Info MakeShaderInfo(Shader::Stage stage, std::span<const u32, 16> user_d
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info.num_user_data = cs_pgm.settings.num_user_regs;
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info.num_user_data = cs_pgm.settings.num_user_regs;
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info.workgroup_size = {cs_pgm.num_thread_x.full, cs_pgm.num_thread_y.full,
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info.workgroup_size = {cs_pgm.num_thread_x.full, cs_pgm.num_thread_y.full,
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cs_pgm.num_thread_z.full};
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cs_pgm.num_thread_z.full};
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info.tgid_enable = {cs_pgm.IsTgidEnabled(0), cs_pgm.IsTgidEnabled(1),
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cs_pgm.IsTgidEnabled(2)};
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info.shared_memory_size = cs_pgm.SharedMemSize();
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info.shared_memory_size = cs_pgm.SharedMemSize();
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break;
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break;
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}
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}
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