video_core: Various fixes (#423)
* video_core: Various fixes * clang format
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@ -360,7 +360,6 @@ int PS4_SYSV_ABI posix_connect() {
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}
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int PS4_SYSV_ABI _sigprocmask() {
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LOG_DEBUG(Lib_Kernel, "STUBBED");
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return ORBIS_OK;
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}
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@ -162,7 +162,7 @@ T Translator::GetSrc(const InstOperand& operand) {
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}
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} else {
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if (operand.input_modifier.abs) {
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UNREACHABLE();
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LOG_WARNING(Render_Vulkan, "Input abs modifier on integer instruction");
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}
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if (operand.input_modifier.neg) {
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UNREACHABLE();
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@ -494,6 +494,13 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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const auto tsharp = TrackSharp(tsharp_handle);
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const auto image = info.ReadUd<AmdGpu::Image>(tsharp.sgpr_base, tsharp.dword_offset);
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const auto inst_info = inst.Flags<IR::TextureInstInfo>();
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if (!image.Valid()) {
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LOG_ERROR(Render_Vulkan, "Shader compiled with unbound image!");
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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inst.ReplaceUsesWith(
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ir.CompositeConstruct(ir.Imm32(0.f), ir.Imm32(0.f), ir.Imm32(0.f), ir.Imm32(0.f)));
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return;
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}
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ASSERT(image.GetType() != AmdGpu::ImageType::Invalid);
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u32 image_binding = descriptors.Add(ImageResource{
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.sgpr_base = tsharp.sgpr_base,
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@ -408,7 +408,7 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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}
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case PM4ItOpcode::WaitRegMem: {
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const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
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ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
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// ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
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// Optimization: VO label waits are special because the emulator
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// will write to the label when presentation is finished. So if
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// there are no other submits to yield to we can sleep the thread
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@ -867,6 +867,33 @@ struct Liverpool {
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}
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};
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union ShaderStageEnable {
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u32 raw;
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BitField<0, 2, u32> ls_en;
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BitField<2, 1, u32> hs_en;
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BitField<3, 2, u32> es_en;
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BitField<5, 1, u32> gs_en;
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BitField<6, 1, u32> vs_en;
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bool IsStageEnabled(u32 stage) {
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switch (stage) {
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case 0:
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case 1:
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return true;
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case 2:
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return gs_en.Value();
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case 3:
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return es_en.Value();
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case 4:
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return hs_en.Value();
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case 5:
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return ls_en.Value();
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default:
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UNREACHABLE();
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}
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}
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};
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union Regs {
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struct {
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INSERT_PADDING_WORDS(0x2C08);
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@ -945,7 +972,9 @@ struct Liverpool {
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INSERT_PADDING_WORDS(0xA2A8 - 0xA2A1 - 1);
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u32 vgt_instance_step_rate_0;
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u32 vgt_instance_step_rate_1;
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INSERT_PADDING_WORDS(0xA2DF - 0xA2A9 - 1);
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INSERT_PADDING_WORDS(0xA2D5 - 0xA2A9 - 1);
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ShaderStageEnable stage_enable;
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INSERT_PADDING_WORDS(9);
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PolygonOffset poly_offset;
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INSERT_PADDING_WORDS(0xA2F8 - 0xA2DF - 5);
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AaConfig aa_config;
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@ -1140,6 +1169,7 @@ static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
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static_assert(GFX6_3D_REG_INDEX(enable_primitive_id) == 0xA2A1);
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static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_0) == 0xA2A8);
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static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_1) == 0xA2A9);
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static_assert(GFX6_3D_REG_INDEX(stage_enable) == 0xA2D5);
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static_assert(GFX6_3D_REG_INDEX(poly_offset) == 0xA2DF);
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static_assert(GFX6_3D_REG_INDEX(aa_config) == 0xA2F8);
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static_assert(GFX6_3D_REG_INDEX(color_buffers[0].base_address) == 0xA318);
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@ -81,6 +81,8 @@ vk::PrimitiveTopology PrimitiveType(Liverpool::PrimitiveType type) {
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return vk::PrimitiveTopology::eTriangleListWithAdjacency;
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case Liverpool::PrimitiveType::AdjTriangleStrip:
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return vk::PrimitiveTopology::eTriangleStripWithAdjacency;
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case Liverpool::PrimitiveType::PatchPrimitive:
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return vk::PrimitiveTopology::ePatchList;
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case Liverpool::PrimitiveType::QuadList:
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// Needs to generate index buffer on the fly.
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return vk::PrimitiveTopology::eTriangleList;
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@ -115,6 +115,10 @@ PipelineCache::PipelineCache(const Instance& instance_, Scheduler& scheduler_,
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}
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const GraphicsPipeline* PipelineCache::GetGraphicsPipeline() {
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// Tessellation is unsupported so skip the draw to avoid locking up the driver.
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if (liverpool->regs.primitive_type == Liverpool::PrimitiveType::PatchPrimitive) {
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return nullptr;
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}
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RefreshGraphicsKey();
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const auto [it, is_new] = graphics_pipelines.try_emplace(graphics_key);
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if (is_new) {
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@ -203,6 +207,10 @@ void PipelineCache::RefreshGraphicsKey() {
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}
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for (u32 i = 0; i < MaxShaderStages; i++) {
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if (!regs.stage_enable.IsStageEnabled(i)) {
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key.stage_hashes[i] = 0;
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continue;
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}
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auto* pgm = regs.ProgramForStage(i);
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if (!pgm || !pgm->Address<u32*>()) {
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key.stage_hashes[i] = 0;
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