amdgpu: tiling mode introduced
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@ -6,6 +6,7 @@
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/types.h"
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#include "resource.h"
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#include "video_core/amdgpu/pixel_format.h"
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#include <array>
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@ -622,7 +623,7 @@ struct Liverpool {
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BitField<19, 1, u32> cmask_is_linear;
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} info;
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union {
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BitField<0, 5, u32> tile_mode_index;
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BitField<0, 5, TilingMode> tile_mode_index;
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BitField<5, 5, u32> fmask_tile_mode_index;
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BitField<12, 3, u32> num_samples_log2;
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BitField<15, 3, u32> num_fragments_log2;
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@ -661,6 +662,22 @@ struct Liverpool {
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return u64(cmask_base_address) << 8;
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}
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[[nodiscard]] size_t GetSizeAligned() const {
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const auto num_bytes_per_element = NumBits(info.format) / 8u;
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const auto slice_size = (slice.tile_max + 1) * 64u;
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const auto total_size = slice_size * (view.slice_max + 1) * num_bytes_per_element;
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ASSERT(total_size > 0);
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return total_size;
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}
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[[nodiscard]] TilingMode GetTilingMode() const {
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return attrib.tile_mode_index;
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}
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[[nodiscard]] bool IsTiled() const {
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return !info.linear_general;
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}
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NumberFormat NumFormat() const {
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// There is a small difference between T# and CB number types, account for it.
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return info.number_type == AmdGpu::NumberFormat::Uscaled ? AmdGpu::NumberFormat::Srgb
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@ -85,6 +85,12 @@ constexpr std::string_view NameOf(ImageType type) {
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}
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}
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enum class TilingMode : u32 {
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Display_Linear = 0x8u,
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Display_MacroTiled = 0xAu,
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Texture_MicroTiled = 0xDu,
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};
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struct Image {
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union {
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BitField<0, 38, u64> base_address;
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@ -122,7 +128,7 @@ struct Image {
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}
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u32 Pitch() const {
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return pitch;
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return pitch + 1;
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}
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u32 NumLayers() const {
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@ -140,6 +146,19 @@ struct Image {
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NumberFormat GetNumberFmt() const noexcept {
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return static_cast<NumberFormat>(num_format.Value());
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}
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[[nodiscard]] TilingMode GetTilingMode() const {
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return static_cast<TilingMode>(tiling_index.Value());
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}
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[[nodiscard]] bool IsTiled() const {
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return GetTilingMode() != TilingMode::Display_Linear;
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}
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[[nodiscard]] size_t GetSizeAligned() const {
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// TODO: Derive this properly from tiling params
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return (width + 1) * (height + 1) * NumComponents(GetDataFmt());
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}
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};
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// 8.2.7. Image Sampler [RDNA 2 Instruction Set Architecture]
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@ -86,18 +86,19 @@ ImageInfo::ImageInfo(const Libraries::VideoOut::BufferAttributeGroup& group) noe
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ImageInfo::ImageInfo(const AmdGpu::Liverpool::ColorBuffer& buffer,
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const AmdGpu::Liverpool::CbDbExtent& hint /*= {}*/) noexcept {
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is_tiled = true;
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is_tiled = buffer.IsTiled();
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pixel_format = LiverpoolToVK::SurfaceFormat(buffer.info.format, buffer.NumFormat());
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type = vk::ImageType::e2D;
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size.width = hint.Valid() ? hint.width : buffer.Pitch();
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size.height = hint.Valid() ? hint.height : buffer.Height();
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size.depth = 1;
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pitch = size.width;
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guest_size_bytes = buffer.slice.tile_max * (buffer.view.slice_max + 1);
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guest_size_bytes = buffer.GetSizeAligned();
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}
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ImageInfo::ImageInfo(const AmdGpu::Image& image) noexcept {
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is_tiled = false;
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is_tiled = image.IsTiled();
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tiling_mode = image.GetTilingMode();
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pixel_format = LiverpoolToVK::SurfaceFormat(image.GetDataFmt(), image.GetNumberFmt());
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type = ConvertImageType(image.type);
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size.width = image.width + 1;
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@ -106,8 +107,7 @@ ImageInfo::ImageInfo(const AmdGpu::Image& image) noexcept {
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pitch = image.Pitch();
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resources.levels = image.NumLevels();
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resources.layers = image.NumLayers();
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// TODO: Derive this properly from tiling params
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guest_size_bytes = size.width * size.height * 4;
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guest_size_bytes = image.GetSizeAligned();
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}
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UniqueImage::UniqueImage(vk::Device device_, VmaAllocator allocator_)
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@ -45,6 +45,7 @@ struct ImageInfo {
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Extent3D size{1, 1, 1};
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u32 pitch = 0;
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u32 guest_size_bytes = 0;
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AmdGpu::TilingMode tiling_mode{AmdGpu::TilingMode::Display_Linear};
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};
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struct UniqueImage {
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