shader_recompiler: Normal gathers
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53fb73e95f
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cd009cfec6
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@ -9,6 +9,9 @@ namespace Shader::Backend::SPIRV {
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struct ImageOperands {
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void Add(spv::ImageOperandsMask new_mask, Id value) {
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if (!Sirit::ValidId(value)) {
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return;
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}
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mask = static_cast<spv::ImageOperandsMask>(static_cast<u32>(mask) |
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static_cast<u32>(new_mask));
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operands.push_back(value);
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@ -25,9 +28,7 @@ Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id c
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const Id sampler = ctx.OpLoad(ctx.sampler_type, ctx.samplers[handle >> 16]);
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const Id sampled_image = ctx.OpSampledImage(texture.sampled_type, image, sampler);
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ImageOperands operands;
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if (Sirit::ValidId(offset)) {
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operands.Add(spv::ImageOperandsMask::ConstOffset, offset);
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}
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operands.Add(spv::ImageOperandsMask::Offset, offset);
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return ctx.OpImageSampleImplicitLod(ctx.F32[4], sampled_image, coords, operands.mask,
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operands.operands);
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}
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@ -61,18 +62,30 @@ Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle,
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spv::ImageOperandsMask::Lod, ctx.ConstF32(0.f));
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}
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Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
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const IR::Value& offset, const IR::Value& offset2) {
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UNREACHABLE_MSG("SPIR-V Instruction");
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}
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Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords,
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const IR::Value& offset, const IR::Value& offset2, Id dref) {
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Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords,
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Id offset, Id offset2) {
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const auto& texture = ctx.images[handle & 0xFFFF];
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const Id image = ctx.OpLoad(texture.image_type, texture.id);
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const Id sampler = ctx.OpLoad(ctx.sampler_type, ctx.samplers[handle >> 16]);
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const Id sampled_image = ctx.OpSampledImage(texture.sampled_type, image, sampler);
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return ctx.OpImageDrefGather(ctx.F32[4], sampled_image, coords, dref);
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const u32 comp = inst->Flags<IR::TextureInstInfo>().gather_comp.Value();
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ImageOperands operands;
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operands.Add(spv::ImageOperandsMask::Offset, offset);
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operands.Add(spv::ImageOperandsMask::Lod, ctx.ConstF32(0.f));
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return ctx.OpImageGather(ctx.F32[4], sampled_image, coords, ctx.ConstU32(comp),
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operands.mask, operands.operands);
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}
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Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords,
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Id offset, Id offset2, Id dref) {
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const auto& texture = ctx.images[handle & 0xFFFF];
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const Id image = ctx.OpLoad(texture.image_type, texture.id);
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const Id sampler = ctx.OpLoad(ctx.sampler_type, ctx.samplers[handle >> 16]);
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const Id sampled_image = ctx.OpSampledImage(texture.sampled_type, image, sampler);
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ImageOperands operands;
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operands.Add(spv::ImageOperandsMask::Offset, offset);
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return ctx.OpImageDrefGather(ctx.F32[4], sampled_image, coords, dref,
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operands.mask, operands.operands);
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}
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Id EmitImageFetch(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id offset, Id lod,
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@ -358,10 +358,10 @@ Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle,
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Id bias_lc, const IR::Value& offset);
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Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id dref,
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Id bias_lc, Id offset);
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Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
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const IR::Value& offset, const IR::Value& offset2);
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Id EmitImageGather(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords,
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Id offset, Id offset2);
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Id EmitImageGatherDref(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords,
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const IR::Value& offset, const IR::Value& offset2, Id dref);
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Id offset, Id offset2, Id dref);
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Id EmitImageFetch(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id offset, Id lod,
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Id ms);
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Id EmitImageQueryDimensions(EmitContext& ctx, IR::Inst* inst, u32 handle, Id lod, bool skip_mips);
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@ -456,6 +456,8 @@ void Translate(IR::Block* block, u32 block_base, std::span<const GcnInst> inst_l
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translator.IMAGE_GET_LOD(inst);
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break;
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case Opcode::IMAGE_GATHER4_C:
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case Opcode::IMAGE_GATHER4_LZ:
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case Opcode::IMAGE_GATHER4_LZ_O:
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translator.IMAGE_GATHER(inst);
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break;
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case Opcode::IMAGE_STORE:
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@ -158,6 +158,7 @@ void Translator::IMAGE_GATHER(const GcnInst& inst) {
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info.has_lod_clamp.Assign(flags.test(MimgModifier::LodClamp));
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info.force_level0.Assign(flags.test(MimgModifier::Level0));
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info.explicit_lod.Assign(explicit_lod);
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info.gather_comp.Assign(std::bit_width(mimg.dmask) - 1);
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// Issue IR instruction, leaving unknown fields blank to patch later.
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const IR::Value texel = [&]() -> IR::Value {
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@ -543,7 +543,9 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
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if (inst_info.has_offset) {
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// The offsets are six-bit signed integers: X=[5:0], Y=[13:8], and Z=[21:16].
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const u32 arg_pos = inst_info.is_depth ? 4 : 3;
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const bool is_gather = inst.GetOpcode() == IR::Opcode::ImageGather ||
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inst.GetOpcode() == IR::Opcode::ImageGatherDref;
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const u32 arg_pos = is_gather ? 2 : (inst_info.is_depth ? 4 : 3);
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const IR::Value arg = inst.Arg(arg_pos);
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ASSERT_MSG(arg.Type() == IR::Type::U32, "Unexpected offset type");
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const auto sign_ext = [&](u32 value) { return ir.Imm32(s32(value << 24) >> 24); };
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@ -39,6 +39,7 @@ union TextureInstInfo {
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BitField<3, 1, u32> force_level0;
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BitField<4, 1, u32> explicit_lod;
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BitField<5, 1, u32> has_offset;
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BitField<6, 2, u32> gather_comp;
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};
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union BufferInstInfo {
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@ -420,6 +420,10 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
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num_format == AmdGpu::NumberFormat::Uint) {
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return vk::Format::eR32G32B32A32Uint;
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}
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if (data_format == AmdGpu::DataFormat::Format32_32_32_32 &&
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num_format == AmdGpu::NumberFormat::Sint) {
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return vk::Format::eR32G32B32A32Sint;
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}
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if (data_format == AmdGpu::DataFormat::Format8 && num_format == AmdGpu::NumberFormat::Sint) {
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return vk::Format::eR8Sint;
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}
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