Handle PM4 type-2 packets (#556)
* video_core: handle PM4 type-2 packets * video_core: rewrite pm4 comand type handling into a switch statement
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@ -175,294 +175,305 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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while (!dcb.empty()) {
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const auto* header = reinterpret_cast<const PM4Header*>(dcb.data());
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const u32 type = header->type;
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if (type != 3) {
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// No other types of packets were spotted so far
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UNREACHABLE_MSG("Invalid PM4 type {}", type);
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}
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const u32 count = header->type3.NumWords();
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const PM4ItOpcode opcode = header->type3.opcode;
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switch (opcode) {
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case PM4ItOpcode::Nop: {
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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if (nop->header.count.Value() == 0) {
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break;
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}
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switch (type) {
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case 0:
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case 1:
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UNREACHABLE_MSG("Unsupported PM4 type {}", type);
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break;
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case 2:
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// Type-2 packet are used for padding purposes
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dcb = dcb.subspan(1);
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continue;
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case 3:
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const u32 count = header->type3.NumWords();
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const PM4ItOpcode opcode = header->type3.opcode;
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switch (opcode) {
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case PM4ItOpcode::Nop: {
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const auto* nop = reinterpret_cast<const PM4CmdNop*>(header);
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if (nop->header.count.Value() == 0) {
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break;
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}
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switch (nop->data_block[0]) {
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case PM4CmdNop::PayloadType::PatchedFlip: {
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// There is no evidence that GPU CP drives flip events by parsing
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// special NOP packets. For convenience lets assume that it does.
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Platform::IrqC::Instance()->Signal(Platform::InterruptId::GfxFlip);
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switch (nop->data_block[0]) {
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case PM4CmdNop::PayloadType::PatchedFlip: {
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// There is no evidence that GPU CP drives flip events by parsing
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// special NOP packets. For convenience lets assume that it does.
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Platform::IrqC::Instance()->Signal(Platform::InterruptId::GfxFlip);
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break;
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}
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case PM4CmdNop::PayloadType::DebugMarkerPush: {
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const auto marker_sz = nop->header.count.Value() * 2;
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const std::string_view label{reinterpret_cast<const char*>(&nop->data_block[1]),
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marker_sz};
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rasterizer->ScopeMarkerBegin(label);
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break;
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}
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case PM4CmdNop::PayloadType::DebugMarkerPop: {
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rasterizer->ScopeMarkerEnd();
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break;
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}
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default:
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break;
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}
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break;
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}
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case PM4CmdNop::PayloadType::DebugMarkerPush: {
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const auto marker_sz = nop->header.count.Value() * 2;
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const std::string_view label{reinterpret_cast<const char*>(&nop->data_block[1]),
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marker_sz};
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rasterizer->ScopeMarkerBegin(label);
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case PM4ItOpcode::ContextControl: {
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break;
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}
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case PM4CmdNop::PayloadType::DebugMarkerPop: {
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rasterizer->ScopeMarkerEnd();
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case PM4ItOpcode::ClearState: {
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regs.SetDefaults();
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break;
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}
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case PM4ItOpcode::SetConfigReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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const auto reg_addr = ConfigRegWordOffset + set_data->reg_offset;
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const auto* payload = reinterpret_cast<const u32*>(header + 2);
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std::memcpy(®s.reg_array[reg_addr], payload, (count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetContextReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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const auto reg_addr = ContextRegWordOffset + set_data->reg_offset;
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const auto* payload = reinterpret_cast<const u32*>(header + 2);
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std::memcpy(®s.reg_array[reg_addr], payload, (count - 1) * sizeof(u32));
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// In the case of HW, render target memory has alignment as color block operates on
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// tiles. There is no information of actual resource extents stored in CB context
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// regs, so any deduction of it from slices/pitch will lead to a larger surface
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// created. The same applies to the depth targets. Fortunately, the guest always
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// sends a trailing NOP packet right after the context regs setup, so we can use the
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// heuristic below and extract the hint to determine actual resource dims.
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switch (reg_addr) {
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case ContextRegs::CbColor0Base:
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case ContextRegs::CbColor1Base:
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case ContextRegs::CbColor2Base:
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case ContextRegs::CbColor3Base:
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case ContextRegs::CbColor4Base:
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case ContextRegs::CbColor5Base:
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case ContextRegs::CbColor6Base:
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case ContextRegs::CbColor7Base: {
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const auto col_buf_id = (reg_addr - ContextRegs::CbColor0Base) /
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(ContextRegs::CbColor1Base - ContextRegs::CbColor0Base);
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ASSERT(col_buf_id < NumColorBuffers);
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const auto nop_offset = header->type3.count;
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if (nop_offset == 0x0e || nop_offset == 0x0d || nop_offset == 0x0b) {
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ASSERT_MSG(payload[nop_offset] == 0xc0001000,
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"NOP hint is missing in CB setup sequence");
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last_cb_extent[col_buf_id].raw = payload[nop_offset + 1];
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} else {
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last_cb_extent[col_buf_id].raw = 0;
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}
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break;
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}
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case ContextRegs::CbColor0Cmask:
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case ContextRegs::CbColor1Cmask:
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case ContextRegs::CbColor2Cmask:
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case ContextRegs::CbColor3Cmask:
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case ContextRegs::CbColor4Cmask:
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case ContextRegs::CbColor5Cmask:
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case ContextRegs::CbColor6Cmask:
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case ContextRegs::CbColor7Cmask: {
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const auto col_buf_id =
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(reg_addr - ContextRegs::CbColor0Cmask) /
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(ContextRegs::CbColor1Cmask - ContextRegs::CbColor0Cmask);
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ASSERT(col_buf_id < NumColorBuffers);
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const auto nop_offset = header->type3.count;
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if (nop_offset == 0x04) {
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ASSERT_MSG(payload[nop_offset] == 0xc0001000,
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"NOP hint is missing in CB setup sequence");
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last_cb_extent[col_buf_id].raw = payload[nop_offset + 1];
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}
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break;
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}
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case ContextRegs::DbZInfo: {
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if (header->type3.count == 8) {
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ASSERT_MSG(payload[20] == 0xc0001000,
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"NOP hint is missing in DB setup sequence");
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last_db_extent.raw = payload[21];
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} else {
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last_db_extent.raw = 0;
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}
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break;
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}
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default:
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break;
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}
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break;
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}
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case PM4ItOpcode::SetShReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2,
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(count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetUconfigReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[UconfigRegWordOffset + set_data->reg_offset],
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header + 2, (count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::IndexType: {
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const auto* index_type = reinterpret_cast<const PM4CmdDrawIndexType*>(header);
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regs.index_buffer_type.raw = index_type->raw;
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break;
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}
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case PM4ItOpcode::DrawIndex2: {
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const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndex2*>(header);
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regs.max_index_size = draw_index->max_size;
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regs.index_base_address.base_addr_lo = draw_index->index_base_lo;
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regs.index_base_address.base_addr_hi.Assign(draw_index->index_base_hi);
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regs.num_indices = draw_index->index_count;
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regs.draw_initiator = draw_index->draw_initiator;
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if (rasterizer) {
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const auto cmd_address = reinterpret_cast<const void*>(header);
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rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:DrawIndex2", cmd_address));
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rasterizer->Breadcrumb(u64(cmd_address));
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rasterizer->Draw(true);
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rasterizer->ScopeMarkerEnd();
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}
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break;
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}
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case PM4ItOpcode::DrawIndexOffset2: {
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const auto* draw_index_off =
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reinterpret_cast<const PM4CmdDrawIndexOffset2*>(header);
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regs.max_index_size = draw_index_off->max_size;
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regs.num_indices = draw_index_off->index_count;
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regs.draw_initiator = draw_index_off->draw_initiator;
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if (rasterizer) {
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const auto cmd_address = reinterpret_cast<const void*>(header);
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rasterizer->ScopeMarkerBegin(
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fmt::format("dcb:{}:DrawIndexOffset2", cmd_address));
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rasterizer->Breadcrumb(u64(cmd_address));
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rasterizer->Draw(true, draw_index_off->index_offset);
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rasterizer->ScopeMarkerEnd();
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}
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break;
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}
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case PM4ItOpcode::DrawIndexAuto: {
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const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndexAuto*>(header);
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regs.num_indices = draw_index->index_count;
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regs.draw_initiator = draw_index->draw_initiator;
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if (rasterizer) {
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const auto cmd_address = reinterpret_cast<const void*>(header);
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rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:DrawIndexAuto", cmd_address));
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rasterizer->Breadcrumb(u64(cmd_address));
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rasterizer->Draw(false);
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rasterizer->ScopeMarkerEnd();
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}
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break;
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}
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case PM4ItOpcode::DispatchDirect: {
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const auto* dispatch_direct = reinterpret_cast<const PM4CmdDispatchDirect*>(header);
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regs.cs_program.dim_x = dispatch_direct->dim_x;
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regs.cs_program.dim_y = dispatch_direct->dim_y;
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regs.cs_program.dim_z = dispatch_direct->dim_z;
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regs.cs_program.dispatch_initiator = dispatch_direct->dispatch_initiator;
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if (rasterizer && (regs.cs_program.dispatch_initiator & 1)) {
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const auto cmd_address = reinterpret_cast<const void*>(header);
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rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:Dispatch", cmd_address));
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rasterizer->Breadcrumb(u64(cmd_address));
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rasterizer->DispatchDirect();
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rasterizer->ScopeMarkerEnd();
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}
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break;
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}
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case PM4ItOpcode::NumInstances: {
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const auto* num_instances = reinterpret_cast<const PM4CmdDrawNumInstances*>(header);
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regs.num_instances.num_instances = num_instances->num_instances;
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break;
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}
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case PM4ItOpcode::IndexBase: {
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const auto* index_base = reinterpret_cast<const PM4CmdDrawIndexBase*>(header);
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regs.index_base_address.base_addr_lo = index_base->addr_lo;
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regs.index_base_address.base_addr_hi.Assign(index_base->addr_hi);
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break;
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}
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case PM4ItOpcode::IndexBufferSize: {
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const auto* index_size = reinterpret_cast<const PM4CmdDrawIndexBufferSize*>(header);
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regs.num_indices = index_size->num_indices;
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break;
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}
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case PM4ItOpcode::EventWrite: {
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// const auto* event = reinterpret_cast<const PM4CmdEventWrite*>(header);
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break;
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}
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case PM4ItOpcode::EventWriteEos: {
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const auto* event_eos = reinterpret_cast<const PM4CmdEventWriteEos*>(header);
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event_eos->SignalFence();
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break;
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}
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case PM4ItOpcode::EventWriteEop: {
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const auto* event_eop = reinterpret_cast<const PM4CmdEventWriteEop*>(header);
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event_eop->SignalFence();
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break;
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}
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case PM4ItOpcode::DmaData: {
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const auto* dma_data = reinterpret_cast<const PM4DmaData*>(header);
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break;
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}
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case PM4ItOpcode::WriteData: {
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const auto* write_data = reinterpret_cast<const PM4CmdWriteData*>(header);
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ASSERT(write_data->dst_sel.Value() == 2 || write_data->dst_sel.Value() == 5);
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const u32 data_size = (header->type3.count.Value() - 2) * 4;
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u64* address = write_data->Address<u64*>();
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if (!write_data->wr_one_addr.Value()) {
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std::memcpy(address, write_data->data, data_size);
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} else {
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UNREACHABLE();
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}
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break;
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}
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case PM4ItOpcode::AcquireMem: {
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// const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header);
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break;
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}
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case PM4ItOpcode::WaitRegMem: {
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const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
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// ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
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// Optimization: VO label waits are special because the emulator
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// will write to the label when presentation is finished. So if
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// there are no other submits to yield to we can sleep the thread
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// instead and allow other tasks to run.
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const u64* wait_addr = wait_reg_mem->Address<u64*>();
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if (vo_port->IsVoLabel(wait_addr) && num_submits == 1) {
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vo_port->WaitVoLabel([&] { return wait_reg_mem->Test(); });
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}
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while (!wait_reg_mem->Test()) {
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mapped_queues[GfxQueueId].cs_state = regs.cs_program;
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TracyFiberLeave;
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co_yield {};
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TracyFiberEnter(dcb_task_name);
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regs.cs_program = mapped_queues[GfxQueueId].cs_state;
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}
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break;
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}
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case PM4ItOpcode::IncrementDeCounter: {
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++cblock.de_count;
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break;
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}
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case PM4ItOpcode::WaitOnCeCounter: {
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while (cblock.ce_count <= cblock.de_count) {
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TracyFiberLeave;
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ce_task.handle.resume();
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TracyFiberEnter(dcb_task_name);
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}
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break;
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}
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case PM4ItOpcode::PfpSyncMe: {
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break;
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}
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default:
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break;
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UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
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static_cast<u32>(opcode), count);
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}
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dcb = dcb.subspan(header->type3.NumWords() + 1);
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break;
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}
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case PM4ItOpcode::ContextControl: {
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break;
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}
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case PM4ItOpcode::ClearState: {
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regs.SetDefaults();
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break;
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}
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case PM4ItOpcode::SetConfigReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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const auto reg_addr = ConfigRegWordOffset + set_data->reg_offset;
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const auto* payload = reinterpret_cast<const u32*>(header + 2);
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std::memcpy(®s.reg_array[reg_addr], payload, (count - 1) * sizeof(u32));
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break;
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}
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case PM4ItOpcode::SetContextReg: {
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const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
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const auto reg_addr = ContextRegWordOffset + set_data->reg_offset;
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const auto* payload = reinterpret_cast<const u32*>(header + 2);
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std::memcpy(®s.reg_array[reg_addr], payload, (count - 1) * sizeof(u32));
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// In the case of HW, render target memory has alignment as color block operates on
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// tiles. There is no information of actual resource extents stored in CB context
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// regs, so any deduction of it from slices/pitch will lead to a larger surface created.
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// The same applies to the depth targets. Fortunately, the guest always sends
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// a trailing NOP packet right after the context regs setup, so we can use the heuristic
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// below and extract the hint to determine actual resource dims.
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switch (reg_addr) {
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case ContextRegs::CbColor0Base:
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case ContextRegs::CbColor1Base:
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case ContextRegs::CbColor2Base:
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case ContextRegs::CbColor3Base:
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case ContextRegs::CbColor4Base:
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case ContextRegs::CbColor5Base:
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case ContextRegs::CbColor6Base:
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case ContextRegs::CbColor7Base: {
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const auto col_buf_id = (reg_addr - ContextRegs::CbColor0Base) /
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(ContextRegs::CbColor1Base - ContextRegs::CbColor0Base);
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ASSERT(col_buf_id < NumColorBuffers);
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const auto nop_offset = header->type3.count;
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if (nop_offset == 0x0e || nop_offset == 0x0d || nop_offset == 0x0b) {
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ASSERT_MSG(payload[nop_offset] == 0xc0001000,
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"NOP hint is missing in CB setup sequence");
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last_cb_extent[col_buf_id].raw = payload[nop_offset + 1];
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} else {
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last_cb_extent[col_buf_id].raw = 0;
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}
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break;
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}
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case ContextRegs::CbColor0Cmask:
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case ContextRegs::CbColor1Cmask:
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case ContextRegs::CbColor2Cmask:
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case ContextRegs::CbColor3Cmask:
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case ContextRegs::CbColor4Cmask:
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case ContextRegs::CbColor5Cmask:
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case ContextRegs::CbColor6Cmask:
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case ContextRegs::CbColor7Cmask: {
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const auto col_buf_id = (reg_addr - ContextRegs::CbColor0Cmask) /
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(ContextRegs::CbColor1Cmask - ContextRegs::CbColor0Cmask);
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ASSERT(col_buf_id < NumColorBuffers);
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const auto nop_offset = header->type3.count;
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if (nop_offset == 0x04) {
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ASSERT_MSG(payload[nop_offset] == 0xc0001000,
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"NOP hint is missing in CB setup sequence");
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last_cb_extent[col_buf_id].raw = payload[nop_offset + 1];
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}
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break;
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}
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case ContextRegs::DbZInfo: {
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if (header->type3.count == 8) {
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ASSERT_MSG(payload[20] == 0xc0001000,
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"NOP hint is missing in DB setup sequence");
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last_db_extent.raw = payload[21];
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} else {
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last_db_extent.raw = 0;
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}
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break;
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||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::SetShReg: {
|
||||
const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
|
||||
std::memcpy(®s.reg_array[ShRegWordOffset + set_data->reg_offset], header + 2,
|
||||
(count - 1) * sizeof(u32));
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::SetUconfigReg: {
|
||||
const auto* set_data = reinterpret_cast<const PM4CmdSetData*>(header);
|
||||
std::memcpy(®s.reg_array[UconfigRegWordOffset + set_data->reg_offset], header + 2,
|
||||
(count - 1) * sizeof(u32));
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::IndexType: {
|
||||
const auto* index_type = reinterpret_cast<const PM4CmdDrawIndexType*>(header);
|
||||
regs.index_buffer_type.raw = index_type->raw;
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::DrawIndex2: {
|
||||
const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndex2*>(header);
|
||||
regs.max_index_size = draw_index->max_size;
|
||||
regs.index_base_address.base_addr_lo = draw_index->index_base_lo;
|
||||
regs.index_base_address.base_addr_hi.Assign(draw_index->index_base_hi);
|
||||
regs.num_indices = draw_index->index_count;
|
||||
regs.draw_initiator = draw_index->draw_initiator;
|
||||
if (rasterizer) {
|
||||
const auto cmd_address = reinterpret_cast<const void*>(header);
|
||||
rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:DrawIndex2", cmd_address));
|
||||
rasterizer->Breadcrumb(u64(cmd_address));
|
||||
rasterizer->Draw(true);
|
||||
rasterizer->ScopeMarkerEnd();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::DrawIndexOffset2: {
|
||||
const auto* draw_index_off = reinterpret_cast<const PM4CmdDrawIndexOffset2*>(header);
|
||||
regs.max_index_size = draw_index_off->max_size;
|
||||
regs.num_indices = draw_index_off->index_count;
|
||||
regs.draw_initiator = draw_index_off->draw_initiator;
|
||||
if (rasterizer) {
|
||||
const auto cmd_address = reinterpret_cast<const void*>(header);
|
||||
rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:DrawIndexOffset2", cmd_address));
|
||||
rasterizer->Breadcrumb(u64(cmd_address));
|
||||
rasterizer->Draw(true, draw_index_off->index_offset);
|
||||
rasterizer->ScopeMarkerEnd();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::DrawIndexAuto: {
|
||||
const auto* draw_index = reinterpret_cast<const PM4CmdDrawIndexAuto*>(header);
|
||||
regs.num_indices = draw_index->index_count;
|
||||
regs.draw_initiator = draw_index->draw_initiator;
|
||||
if (rasterizer) {
|
||||
const auto cmd_address = reinterpret_cast<const void*>(header);
|
||||
rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:DrawIndexAuto", cmd_address));
|
||||
rasterizer->Breadcrumb(u64(cmd_address));
|
||||
rasterizer->Draw(false);
|
||||
rasterizer->ScopeMarkerEnd();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::DispatchDirect: {
|
||||
const auto* dispatch_direct = reinterpret_cast<const PM4CmdDispatchDirect*>(header);
|
||||
regs.cs_program.dim_x = dispatch_direct->dim_x;
|
||||
regs.cs_program.dim_y = dispatch_direct->dim_y;
|
||||
regs.cs_program.dim_z = dispatch_direct->dim_z;
|
||||
regs.cs_program.dispatch_initiator = dispatch_direct->dispatch_initiator;
|
||||
if (rasterizer && (regs.cs_program.dispatch_initiator & 1)) {
|
||||
const auto cmd_address = reinterpret_cast<const void*>(header);
|
||||
rasterizer->ScopeMarkerBegin(fmt::format("dcb:{}:Dispatch", cmd_address));
|
||||
rasterizer->Breadcrumb(u64(cmd_address));
|
||||
rasterizer->DispatchDirect();
|
||||
rasterizer->ScopeMarkerEnd();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::NumInstances: {
|
||||
const auto* num_instances = reinterpret_cast<const PM4CmdDrawNumInstances*>(header);
|
||||
regs.num_instances.num_instances = num_instances->num_instances;
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::IndexBase: {
|
||||
const auto* index_base = reinterpret_cast<const PM4CmdDrawIndexBase*>(header);
|
||||
regs.index_base_address.base_addr_lo = index_base->addr_lo;
|
||||
regs.index_base_address.base_addr_hi.Assign(index_base->addr_hi);
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::IndexBufferSize: {
|
||||
const auto* index_size = reinterpret_cast<const PM4CmdDrawIndexBufferSize*>(header);
|
||||
regs.num_indices = index_size->num_indices;
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::EventWrite: {
|
||||
// const auto* event = reinterpret_cast<const PM4CmdEventWrite*>(header);
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::EventWriteEos: {
|
||||
const auto* event_eos = reinterpret_cast<const PM4CmdEventWriteEos*>(header);
|
||||
event_eos->SignalFence();
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::EventWriteEop: {
|
||||
const auto* event_eop = reinterpret_cast<const PM4CmdEventWriteEop*>(header);
|
||||
event_eop->SignalFence();
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::DmaData: {
|
||||
const auto* dma_data = reinterpret_cast<const PM4DmaData*>(header);
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::WriteData: {
|
||||
const auto* write_data = reinterpret_cast<const PM4CmdWriteData*>(header);
|
||||
ASSERT(write_data->dst_sel.Value() == 2 || write_data->dst_sel.Value() == 5);
|
||||
const u32 data_size = (header->type3.count.Value() - 2) * 4;
|
||||
u64* address = write_data->Address<u64*>();
|
||||
if (!write_data->wr_one_addr.Value()) {
|
||||
std::memcpy(address, write_data->data, data_size);
|
||||
} else {
|
||||
UNREACHABLE();
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::AcquireMem: {
|
||||
// const auto* acquire_mem = reinterpret_cast<PM4CmdAcquireMem*>(header);
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::WaitRegMem: {
|
||||
const auto* wait_reg_mem = reinterpret_cast<const PM4CmdWaitRegMem*>(header);
|
||||
// ASSERT(wait_reg_mem->engine.Value() == PM4CmdWaitRegMem::Engine::Me);
|
||||
// Optimization: VO label waits are special because the emulator
|
||||
// will write to the label when presentation is finished. So if
|
||||
// there are no other submits to yield to we can sleep the thread
|
||||
// instead and allow other tasks to run.
|
||||
const u64* wait_addr = wait_reg_mem->Address<u64*>();
|
||||
if (vo_port->IsVoLabel(wait_addr) && num_submits == 1) {
|
||||
vo_port->WaitVoLabel([&] { return wait_reg_mem->Test(); });
|
||||
}
|
||||
while (!wait_reg_mem->Test()) {
|
||||
mapped_queues[GfxQueueId].cs_state = regs.cs_program;
|
||||
TracyFiberLeave;
|
||||
co_yield {};
|
||||
TracyFiberEnter(dcb_task_name);
|
||||
regs.cs_program = mapped_queues[GfxQueueId].cs_state;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::IncrementDeCounter: {
|
||||
++cblock.de_count;
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::WaitOnCeCounter: {
|
||||
while (cblock.ce_count <= cblock.de_count) {
|
||||
TracyFiberLeave;
|
||||
ce_task.handle.resume();
|
||||
TracyFiberEnter(dcb_task_name);
|
||||
}
|
||||
break;
|
||||
}
|
||||
case PM4ItOpcode::PfpSyncMe: {
|
||||
break;
|
||||
}
|
||||
default:
|
||||
UNREACHABLE_MSG("Unknown PM4 type 3 opcode {:#x} with count {}",
|
||||
static_cast<u32>(opcode), count);
|
||||
}
|
||||
dcb = dcb.subspan(header->type3.NumWords() + 1);
|
||||
}
|
||||
|
||||
if (ce_task.handle) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue