Merge pull request #190 from shadps4-emu/stabilization_three

Stabilization three
This commit is contained in:
georgemoralis 2024-06-11 07:25:55 +03:00 committed by GitHub
commit bff2f006fb
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6 changed files with 41 additions and 6 deletions

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@ -9,9 +9,16 @@
#include "core/libraries/libs.h"
#ifdef _WIN64
#include <Windows.h>
#include <pthread_time.h>
// http://stackoverflow.com/a/31411628/4725495
static u32(__stdcall* NtDelayExecution)(BOOL Alertable, PLARGE_INTEGER DelayInterval) =
(u32(__stdcall*)(BOOL, PLARGE_INTEGER))GetProcAddress(GetModuleHandle("ntdll.dll"),
"NtDelayExecution");
#else
#include <time.h>
#include <unistd.h>
#endif
namespace Libraries::Kernel {
@ -40,8 +47,18 @@ u64 PS4_SYSV_ABI sceKernelReadTsc() {
}
int PS4_SYSV_ABI sceKernelUsleep(u32 microseconds) {
ASSERT(microseconds >= 1000);
std::this_thread::sleep_for(std::chrono::microseconds(microseconds));
if (microseconds < 1000u) {
#if _WIN64
LARGE_INTEGER interval{
.QuadPart = -1 * (microseconds * 10u),
};
NtDelayExecution(FALSE, &interval);
} else {
std::this_thread::sleep_for(std::chrono::microseconds(microseconds));
}
#else
usleep(microseconds);
#endif
return 0;
}

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@ -228,6 +228,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
case Opcode::V_AND_B32:
translator.V_AND_B32(inst);
break;
case Opcode::V_OR_B32:
translator.V_OR_B32(inst);
break;
case Opcode::V_LSHLREV_B32:
translator.V_LSHLREV_B32(inst);
break;
@ -318,6 +321,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
case Opcode::V_CMP_EQ_I32:
translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
break;
case Opcode::V_CMP_LE_I32:
translator.V_CMP_U32(ConditionOp::LE, true, false, inst);
break;
case Opcode::V_CMP_NE_U32:
translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
break;
@ -378,6 +384,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
case Opcode::S_CMP_GT_I32:
translator.S_CMP(ConditionOp::GT, true, inst);
break;
case Opcode::S_CMP_GE_I32:
translator.S_CMP(ConditionOp::GE, true, inst);
break;
case Opcode::S_CMP_EQ_I32:
translator.S_CMP(ConditionOp::EQ, true, inst);
break;

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@ -62,6 +62,7 @@ public:
void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
void V_MUL_F32(const GcnInst& inst);
void V_CNDMASK_B32(const GcnInst& inst);
void V_OR_B32(const GcnInst& inst);
void V_AND_B32(const GcnInst& inst);
void V_LSHLREV_B32(const GcnInst& inst);
void V_ADD_I32(const GcnInst& inst);

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@ -50,6 +50,13 @@ void Translator::V_CNDMASK_B32(const GcnInst& inst) {
ir.SetVectorReg(dst_reg, IR::U32F32{result});
}
void Translator::V_OR_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
const IR::VectorReg dst_reg{inst.dst[0].code};
ir.SetVectorReg(dst_reg, ir.BitwiseOr(src0, src1));
}
void Translator::V_AND_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};

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@ -429,8 +429,10 @@ void GraphicsPipeline::BindVertexBuffers(StreamBuffer& staging) const {
for (u32 i = 0; i < num_buffers; ++i) {
const auto& buffer = guest_buffers[i];
const auto& host_buffer = std::ranges::find_if(
ranges_merged.cbegin(), ranges_merged.cend(),
[&](const BufferRange& range) { return (buffer.base_address >= range.base_address); });
ranges_merged.cbegin(), ranges_merged.cend(), [&](const BufferRange& range) {
return (buffer.base_address >= range.base_address &&
buffer.base_address < range.end_address);
});
assert(host_buffer != ranges_merged.cend());
host_buffers[i] = staging.Handle();

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@ -232,8 +232,7 @@ void StreamBuffer::WaitPendingOperations(u64 requested_upper_bound) {
}
u64 StreamBuffer::Copy(VAddr src, size_t size, size_t alignment /*= 0*/) {
static const u64 MinUniformAlignment = instance.UniformMinAlignment();
const auto [data, offset, _] = Map(size, MinUniformAlignment);
const auto [data, offset, _] = Map(size, alignment);
std::memcpy(data, reinterpret_cast<const void*>(src), size);
Commit(size);
return offset;