Merge pull request #190 from shadps4-emu/stabilization_three
Stabilization three
This commit is contained in:
commit
bff2f006fb
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@ -9,9 +9,16 @@
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#include "core/libraries/libs.h"
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#include "core/libraries/libs.h"
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#ifdef _WIN64
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#ifdef _WIN64
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#include <Windows.h>
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#include <pthread_time.h>
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#include <pthread_time.h>
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// http://stackoverflow.com/a/31411628/4725495
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static u32(__stdcall* NtDelayExecution)(BOOL Alertable, PLARGE_INTEGER DelayInterval) =
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(u32(__stdcall*)(BOOL, PLARGE_INTEGER))GetProcAddress(GetModuleHandle("ntdll.dll"),
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"NtDelayExecution");
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#else
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#else
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#include <time.h>
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#include <time.h>
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#include <unistd.h>
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#endif
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#endif
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namespace Libraries::Kernel {
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namespace Libraries::Kernel {
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@ -40,8 +47,18 @@ u64 PS4_SYSV_ABI sceKernelReadTsc() {
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}
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}
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int PS4_SYSV_ABI sceKernelUsleep(u32 microseconds) {
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int PS4_SYSV_ABI sceKernelUsleep(u32 microseconds) {
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ASSERT(microseconds >= 1000);
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if (microseconds < 1000u) {
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std::this_thread::sleep_for(std::chrono::microseconds(microseconds));
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#if _WIN64
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LARGE_INTEGER interval{
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.QuadPart = -1 * (microseconds * 10u),
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};
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NtDelayExecution(FALSE, &interval);
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} else {
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std::this_thread::sleep_for(std::chrono::microseconds(microseconds));
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}
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#else
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usleep(microseconds);
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#endif
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return 0;
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return 0;
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}
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}
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@ -228,6 +228,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_AND_B32:
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case Opcode::V_AND_B32:
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translator.V_AND_B32(inst);
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translator.V_AND_B32(inst);
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break;
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break;
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case Opcode::V_OR_B32:
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translator.V_OR_B32(inst);
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break;
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case Opcode::V_LSHLREV_B32:
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case Opcode::V_LSHLREV_B32:
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translator.V_LSHLREV_B32(inst);
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translator.V_LSHLREV_B32(inst);
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break;
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break;
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@ -318,6 +321,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CMP_EQ_I32:
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case Opcode::V_CMP_EQ_I32:
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translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
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translator.V_CMP_U32(ConditionOp::EQ, true, false, inst);
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break;
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break;
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case Opcode::V_CMP_LE_I32:
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translator.V_CMP_U32(ConditionOp::LE, true, false, inst);
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break;
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case Opcode::V_CMP_NE_U32:
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case Opcode::V_CMP_NE_U32:
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translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
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translator.V_CMP_U32(ConditionOp::LG, false, false, inst);
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break;
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break;
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@ -378,6 +384,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::S_CMP_GT_I32:
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case Opcode::S_CMP_GT_I32:
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translator.S_CMP(ConditionOp::GT, true, inst);
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translator.S_CMP(ConditionOp::GT, true, inst);
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break;
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break;
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case Opcode::S_CMP_GE_I32:
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translator.S_CMP(ConditionOp::GE, true, inst);
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break;
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case Opcode::S_CMP_EQ_I32:
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case Opcode::S_CMP_EQ_I32:
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translator.S_CMP(ConditionOp::EQ, true, inst);
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translator.S_CMP(ConditionOp::EQ, true, inst);
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break;
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break;
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@ -62,6 +62,7 @@ public:
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void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
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void V_CVT_PKRTZ_F16_F32(const GcnInst& inst);
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void V_MUL_F32(const GcnInst& inst);
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void V_MUL_F32(const GcnInst& inst);
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void V_CNDMASK_B32(const GcnInst& inst);
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void V_CNDMASK_B32(const GcnInst& inst);
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void V_OR_B32(const GcnInst& inst);
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void V_AND_B32(const GcnInst& inst);
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void V_AND_B32(const GcnInst& inst);
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void V_LSHLREV_B32(const GcnInst& inst);
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void V_LSHLREV_B32(const GcnInst& inst);
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void V_ADD_I32(const GcnInst& inst);
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void V_ADD_I32(const GcnInst& inst);
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@ -50,6 +50,13 @@ void Translator::V_CNDMASK_B32(const GcnInst& inst) {
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ir.SetVectorReg(dst_reg, IR::U32F32{result});
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ir.SetVectorReg(dst_reg, IR::U32F32{result});
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}
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}
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void Translator::V_OR_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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ir.SetVectorReg(dst_reg, ir.BitwiseOr(src0, src1));
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}
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void Translator::V_AND_B32(const GcnInst& inst) {
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void Translator::V_AND_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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@ -429,8 +429,10 @@ void GraphicsPipeline::BindVertexBuffers(StreamBuffer& staging) const {
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for (u32 i = 0; i < num_buffers; ++i) {
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for (u32 i = 0; i < num_buffers; ++i) {
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const auto& buffer = guest_buffers[i];
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const auto& buffer = guest_buffers[i];
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const auto& host_buffer = std::ranges::find_if(
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const auto& host_buffer = std::ranges::find_if(
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ranges_merged.cbegin(), ranges_merged.cend(),
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ranges_merged.cbegin(), ranges_merged.cend(), [&](const BufferRange& range) {
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[&](const BufferRange& range) { return (buffer.base_address >= range.base_address); });
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return (buffer.base_address >= range.base_address &&
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buffer.base_address < range.end_address);
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});
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assert(host_buffer != ranges_merged.cend());
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assert(host_buffer != ranges_merged.cend());
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host_buffers[i] = staging.Handle();
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host_buffers[i] = staging.Handle();
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@ -232,8 +232,7 @@ void StreamBuffer::WaitPendingOperations(u64 requested_upper_bound) {
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}
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}
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u64 StreamBuffer::Copy(VAddr src, size_t size, size_t alignment /*= 0*/) {
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u64 StreamBuffer::Copy(VAddr src, size_t size, size_t alignment /*= 0*/) {
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static const u64 MinUniformAlignment = instance.UniformMinAlignment();
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const auto [data, offset, _] = Map(size, alignment);
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const auto [data, offset, _] = Map(size, MinUniformAlignment);
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std::memcpy(data, reinterpret_cast<const void*>(src), size);
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std::memcpy(data, reinterpret_cast<const void*>(src), size);
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Commit(size);
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Commit(size);
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return offset;
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return offset;
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