renderer_vulkan: fixed buffers alignments
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1e69f83d9e
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@ -95,8 +95,9 @@ void ComputePipeline::BindResources(Core::MemoryManager* memory, StreamBuffer& s
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const u32 size = vsharp.GetSize();
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const u32 size = vsharp.GetSize();
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const VAddr addr = vsharp.base_address.Value();
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const VAddr addr = vsharp.base_address.Value();
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texture_cache.OnCpuWrite(addr);
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texture_cache.OnCpuWrite(addr);
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const u32 offset =
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const u32 offset = staging.Copy(addr, size,
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staging.Copy(addr, size, buffer.is_storage ? 4 : instance.UniformMinAlignment());
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buffer.is_storage ? instance.StorageMinAlignment()
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: instance.UniformMinAlignment());
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// const auto [vk_buffer, offset] = memory->GetVulkanBuffer(addr);
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// const auto [vk_buffer, offset] = memory->GetVulkanBuffer(addr);
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buffer_infos.emplace_back(staging.Handle(), offset, size);
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buffer_infos.emplace_back(staging.Handle(), offset, size);
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set_writes.push_back({
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set_writes.push_back({
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@ -327,7 +327,8 @@ void GraphicsPipeline::BindResources(Core::MemoryManager* memory, StreamBuffer&
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const auto vsharp = stage.ReadUd<AmdGpu::Buffer>(buffer.sgpr_base, buffer.dword_offset);
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const auto vsharp = stage.ReadUd<AmdGpu::Buffer>(buffer.sgpr_base, buffer.dword_offset);
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const u32 size = vsharp.GetSize();
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const u32 size = vsharp.GetSize();
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const u32 offset = staging.Copy(vsharp.base_address.Value(), size,
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const u32 offset = staging.Copy(vsharp.base_address.Value(), size,
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buffer.is_storage ? 4 : instance.UniformMinAlignment());
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buffer.is_storage ? instance.StorageMinAlignment()
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: instance.UniformMinAlignment());
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buffer_infos.emplace_back(staging.Handle(), offset, size);
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buffer_infos.emplace_back(staging.Handle(), offset, size);
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set_writes.push_back({
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set_writes.push_back({
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.dstSet = VK_NULL_HANDLE,
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.dstSet = VK_NULL_HANDLE,
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@ -213,6 +213,7 @@ bool Instance::CreateDevice() {
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},
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},
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vk::PhysicalDeviceVulkan12Features{
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vk::PhysicalDeviceVulkan12Features{
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.scalarBlockLayout = true,
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.scalarBlockLayout = true,
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.uniformBufferStandardLayout = true,
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.hostQueryReset = true,
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.hostQueryReset = true,
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.timelineSemaphore = true,
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.timelineSemaphore = true,
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},
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},
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@ -169,6 +169,11 @@ public:
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return properties.limits.minUniformBufferOffsetAlignment;
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return properties.limits.minUniformBufferOffsetAlignment;
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}
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}
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/// Returns the minimum required alignment for storage buffers
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vk::DeviceSize StorageMinAlignment() const {
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return properties.limits.minStorageBufferOffsetAlignment;
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}
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/// Returns the minimum alignemt required for accessing host-mapped device memory
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/// Returns the minimum alignemt required for accessing host-mapped device memory
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vk::DeviceSize NonCoherentAtomSize() const {
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vk::DeviceSize NonCoherentAtomSize() const {
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return properties.limits.nonCoherentAtomSize;
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return properties.limits.nonCoherentAtomSize;
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@ -315,7 +315,8 @@ bool TileManager::TryDetile(Image& image) {
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return false;
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return false;
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}
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}
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const auto offset = staging.Copy(image.cpu_addr, image.info.guest_size_bytes, 4);
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const auto offset =
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staging.Copy(image.cpu_addr, image.info.guest_size_bytes, instance.StorageMinAlignment());
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image.Transit(vk::ImageLayout::eGeneral, vk::AccessFlagBits::eShaderWrite);
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image.Transit(vk::ImageLayout::eGeneral, vk::AccessFlagBits::eShaderWrite);
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auto cmdbuf = scheduler.CommandBuffer();
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auto cmdbuf = scheduler.CommandBuffer();
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