From be67fdc9c90e98742256b3d3eccdf44ff94a6e40 Mon Sep 17 00:00:00 2001
From: psucien <bad_cast@protonmail.com>
Date: Sun, 16 Jun 2024 21:21:19 +0200
Subject: [PATCH] shader_recompiler: correct format for SSBO store op

---
 .../backend/spirv/emit_spirv_context_get_set.cpp |  2 +-
 .../frontend/translate/vector_memory.cpp         | 16 ++++++++++------
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
index 99547ff4..4ebbd465 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
@@ -185,7 +185,7 @@ Id EmitLoadBufferF32x4(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address)
 }
 
 void EmitStoreBufferF32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
-    UNREACHABLE();
+    EmitStoreBufferU32(ctx, inst, handle, address, value);
 }
 
 void EmitStoreBufferF32x2(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
diff --git a/src/shader_recompiler/frontend/translate/vector_memory.cpp b/src/shader_recompiler/frontend/translate/vector_memory.cpp
index aad9ba84..00f7fcda 100644
--- a/src/shader_recompiler/frontend/translate/vector_memory.cpp
+++ b/src/shader_recompiler/frontend/translate/vector_memory.cpp
@@ -216,18 +216,22 @@ void Translator::BUFFER_STORE_FORMAT(u32 num_dwords, bool is_typed, const GcnIns
     const IR::VectorReg src_reg{inst.src[1].code};
     switch (num_dwords) {
     case 1:
-        value = ir.GetVectorReg(src_reg);
+        value = ir.GetVectorReg<Shader::IR::F32>(src_reg);
         break;
     case 2:
-        value = ir.CompositeConstruct(ir.GetVectorReg(src_reg), ir.GetVectorReg(src_reg + 1));
+        value = ir.CompositeConstruct(ir.GetVectorReg<Shader::IR::F32>(src_reg),
+                                      ir.GetVectorReg<Shader::IR::F32>(src_reg + 1));
         break;
     case 3:
-        value = ir.CompositeConstruct(ir.GetVectorReg(src_reg), ir.GetVectorReg(src_reg + 1),
-                                      ir.GetVectorReg(src_reg + 2));
+        value = ir.CompositeConstruct(ir.GetVectorReg<Shader::IR::F32>(src_reg),
+                                      ir.GetVectorReg<Shader::IR::F32>(src_reg + 1),
+                                      ir.GetVectorReg<Shader::IR::F32>(src_reg + 2));
         break;
     case 4:
-        value = ir.CompositeConstruct(ir.GetVectorReg(src_reg), ir.GetVectorReg(src_reg + 1),
-                                      ir.GetVectorReg(src_reg + 2), ir.GetVectorReg(src_reg + 3));
+        value = ir.CompositeConstruct(ir.GetVectorReg<Shader::IR::F32>(src_reg),
+                                      ir.GetVectorReg<Shader::IR::F32>(src_reg + 1),
+                                      ir.GetVectorReg<Shader::IR::F32>(src_reg + 2),
+                                      ir.GetVectorReg<Shader::IR::F32>(src_reg + 3));
         break;
     }
     ir.StoreBuffer(num_dwords, ir.GetScalarReg(sharp), address, value, info);