shader_recompiler: constant propagation bitwise operations + S_CMPK_EQ_U32 fix (#613)
* rebase on main branch impl of V_LSHL_B64 * remove V_LSHR_B64 * fix S_CMPK_EQ_u32 * fix conflicts * fix broken merge * remove duplicate cases * remove duplicate declaration
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@ -286,6 +286,7 @@ Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift);
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Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift);
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Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitBitwiseAnd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitBitwiseOr64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
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@ -139,6 +139,13 @@ Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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return result;
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}
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Id EmitBitwiseAnd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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const Id result{ctx.OpBitwiseAnd(ctx.U64, a, b)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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const Id result{ctx.OpBitwiseOr(ctx.U32[1], a, b)};
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SetZeroFlag(ctx, inst, result);
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@ -472,7 +472,7 @@ void Translator::S_MIN_U32(const GcnInst& inst) {
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void Translator::S_CMPK_EQ_U32(const GcnInst& inst) {
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const s32 simm16 = inst.control.sopk.simm;
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src0{GetSrc(inst.dst[0])};
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const IR::U32 src1{ir.Imm32(simm16)};
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ir.SetScc(ir.IEqual(src0, src1));
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}
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@ -1115,8 +1115,18 @@ U32U64 IREmitter::ShiftRightArithmetic(const U32U64& base, const U32& shift) {
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}
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}
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U32 IREmitter::BitwiseAnd(const U32& a, const U32& b) {
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U32U64 IREmitter::BitwiseAnd(const U32U64& a, const U32U64& b) {
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if (a.Type() != b.Type()) {
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UNREACHABLE_MSG("Mismatching types {} and {}", a.Type(), b.Type());
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}
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switch (a.Type()) {
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case Type::U32:
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return Inst<U32>(Opcode::BitwiseAnd32, a, b);
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case Type::U64:
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return Inst<U64>(Opcode::BitwiseAnd64, a, b);
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default:
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ThrowInvalidType(a.Type());
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}
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}
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U32U64 IREmitter::BitwiseOr(const U32U64& a, const U32U64& b) {
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@ -195,7 +195,7 @@ public:
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[[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
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[[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift);
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[[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b);
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[[nodiscard]] U32U64 BitwiseAnd(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32U64 BitwiseOr(const U32U64& a, const U32U64& b);
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[[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b);
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[[nodiscard]] U32 BitFieldInsert(const U32& base, const U32& insert, const U32& offset,
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@ -260,6 +260,7 @@ OPCODE(ShiftRightLogical64, U64, U64,
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OPCODE(ShiftRightArithmetic32, U32, U32, U32, )
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OPCODE(ShiftRightArithmetic64, U64, U64, U32, )
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OPCODE(BitwiseAnd32, U32, U32, U32, )
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OPCODE(BitwiseAnd64, U64, U64, U64, )
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OPCODE(BitwiseOr32, U32, U32, U32, )
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OPCODE(BitwiseOr64, U64, U64, U64, )
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OPCODE(BitwiseXor32, U32, U32, U32, )
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@ -352,9 +352,15 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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case IR::Opcode::BitwiseAnd32:
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FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a & b; });
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return;
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case IR::Opcode::BitwiseAnd64:
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FoldWhenAllImmediates(inst, [](u64 a, u64 b) { return a & b; });
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return;
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case IR::Opcode::BitwiseOr32:
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FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a | b; });
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return;
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case IR::Opcode::BitwiseOr64:
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FoldWhenAllImmediates(inst, [](u64 a, u64 b) { return a | b; });
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return;
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case IR::Opcode::BitwiseXor32:
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FoldWhenAllImmediates(inst, [](u32 a, u32 b) { return a ^ b; });
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return;
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