video_core: added support for indirect dispatches (gfx only)
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3fbb68048e
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9d349a1308
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@ -383,6 +383,22 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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}
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}
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break;
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break;
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}
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}
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case PM4ItOpcode::DispatchIndirect: {
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const auto* dispatch_indirect =
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reinterpret_cast<const PM4CmdDispatchIndirect*>(header);
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const auto offset = dispatch_indirect->data_offset;
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const auto ib_address = mapped_queues[GfxQueueId].indirect_args_addr;
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const auto size = sizeof(PM4CmdDispatchIndirect::GroupDimensions);
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if (rasterizer && (regs.cs_program.dispatch_initiator & 1)) {
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const auto cmd_address = reinterpret_cast<const void*>(header);
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rasterizer->ScopeMarkerBegin(
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fmt::format("dcb:{}:DispatchIndirect", cmd_address));
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rasterizer->Breadcrumb(u64(cmd_address));
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rasterizer->DispatchIndirect(ib_address, offset, size);
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rasterizer->ScopeMarkerEnd();
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}
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break;
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}
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case PM4ItOpcode::NumInstances: {
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case PM4ItOpcode::NumInstances: {
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const auto* num_instances = reinterpret_cast<const PM4CmdDrawNumInstances*>(header);
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const auto* num_instances = reinterpret_cast<const PM4CmdDrawNumInstances*>(header);
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regs.num_instances.num_instances = num_instances->num_instances;
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regs.num_instances.num_instances = num_instances->num_instances;
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@ -399,6 +415,12 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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regs.num_indices = index_size->num_indices;
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regs.num_indices = index_size->num_indices;
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break;
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break;
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}
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}
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case PM4ItOpcode::SetBase: {
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const auto* set_base = reinterpret_cast<const PM4CmdSetBase*>(header);
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ASSERT(set_base->base_index == PM4CmdSetBase::BaseIndex::DrawIndexIndirPatchTable);
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mapped_queues[GfxQueueId].indirect_args_addr = set_base->Address<u64>();
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break;
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}
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case PM4ItOpcode::EventWrite: {
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case PM4ItOpcode::EventWrite: {
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// const auto* event = reinterpret_cast<const PM4CmdEventWrite*>(header);
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// const auto* event = reinterpret_cast<const PM4CmdEventWrite*>(header);
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break;
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break;
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@ -1127,6 +1127,7 @@ private:
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std::vector<u32> ccb_buffer;
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std::vector<u32> ccb_buffer;
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std::queue<Task::Handle> submits{};
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std::queue<Task::Handle> submits{};
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ComputeProgram cs_state{};
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ComputeProgram cs_state{};
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VAddr indirect_args_addr{};
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};
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};
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std::array<GpuQueue, NumTotalQueues> mapped_queues{};
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std::array<GpuQueue, NumTotalQueues> mapped_queues{};
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@ -704,4 +704,40 @@ struct PM4CmdReleaseMem {
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}
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}
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};
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};
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struct PM4CmdSetBase {
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enum class BaseIndex : u32 {
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DisplayListPatchTable = 0b0000,
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DrawIndexIndirPatchTable = 0b0001,
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GdsPartition = 0b0010,
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CePartition = 0b0011,
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};
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PM4Type3Header header;
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union {
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BitField<0, 4, BaseIndex> base_index;
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u32 dw1;
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};
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u32 address0;
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u32 address1;
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template <typename T>
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T Address() const {
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ASSERT(base_index == BaseIndex::DisplayListPatchTable ||
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base_index == BaseIndex::DrawIndexIndirPatchTable);
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return reinterpret_cast<T>(address0 | (u64(address1 & 0xffff) << 32u));
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}
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};
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struct PM4CmdDispatchIndirect {
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struct GroupDimensions {
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u32 dim_x;
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u32 dim_y;
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u32 dim_z;
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};
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PM4Type3Header header;
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u32 data_offset; ///< Byte aligned offset where the required data structure starts
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u32 dispatch_initiator; ///< Dispatch Initiator Register
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};
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} // namespace AmdGpu
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} // namespace AmdGpu
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@ -17,7 +17,8 @@ constexpr vk::BufferUsageFlags AllFlags =
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vk::BufferUsageFlagBits::eTransferSrc | vk::BufferUsageFlagBits::eTransferDst |
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vk::BufferUsageFlagBits::eTransferSrc | vk::BufferUsageFlagBits::eTransferDst |
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vk::BufferUsageFlagBits::eUniformTexelBuffer | vk::BufferUsageFlagBits::eStorageTexelBuffer |
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vk::BufferUsageFlagBits::eUniformTexelBuffer | vk::BufferUsageFlagBits::eStorageTexelBuffer |
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vk::BufferUsageFlagBits::eUniformBuffer | vk::BufferUsageFlagBits::eStorageBuffer |
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vk::BufferUsageFlagBits::eUniformBuffer | vk::BufferUsageFlagBits::eStorageBuffer |
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vk::BufferUsageFlagBits::eIndexBuffer | vk::BufferUsageFlagBits::eVertexBuffer;
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vk::BufferUsageFlagBits::eIndexBuffer | vk::BufferUsageFlagBits::eVertexBuffer |
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vk::BufferUsageFlagBits::eIndirectBuffer;
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std::string_view BufferTypeName(MemoryUsage type) {
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std::string_view BufferTypeName(MemoryUsage type) {
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switch (type) {
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switch (type) {
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@ -90,6 +90,45 @@ void Rasterizer::DispatchDirect() {
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cmdbuf.dispatch(cs_program.dim_x, cs_program.dim_y, cs_program.dim_z);
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cmdbuf.dispatch(cs_program.dim_x, cs_program.dim_y, cs_program.dim_z);
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}
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}
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void Rasterizer::DispatchIndirect(VAddr address, u32 offset, u32 size) {
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RENDERER_TRACE;
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const auto cmdbuf = scheduler.CommandBuffer();
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const auto& cs_program = liverpool->regs.cs_program;
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const ComputePipeline* pipeline = pipeline_cache.GetComputePipeline();
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if (!pipeline) {
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return;
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}
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try {
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const auto has_resources = pipeline->BindResources(buffer_cache, texture_cache);
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if (!has_resources) {
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return;
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}
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} catch (...) {
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UNREACHABLE();
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}
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scheduler.EndRendering();
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cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, pipeline->Handle());
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const auto [buffer, base] = buffer_cache.ObtainBuffer(address, size, true);
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const auto total_offset = base + offset;
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// Emulate PFP-to-ME sync packet
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const vk::BufferMemoryBarrier ib_barrier{
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.srcAccessMask = vk::AccessFlagBits::eShaderWrite,
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.dstAccessMask = vk::AccessFlagBits::eIndirectCommandRead,
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.buffer = buffer->Handle(),
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.offset = total_offset,
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.size = size,
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};
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cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eComputeShader,
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vk::PipelineStageFlagBits::eDrawIndirect,
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vk::DependencyFlagBits::eByRegion, {}, ib_barrier, {});
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cmdbuf.dispatchIndirect(buffer->Handle(), total_offset);
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}
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u64 Rasterizer::Flush() {
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u64 Rasterizer::Flush() {
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const u64 current_tick = scheduler.CurrentTick();
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const u64 current_tick = scheduler.CurrentTick();
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SubmitInfo info{};
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SubmitInfo info{};
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@ -34,6 +34,7 @@ public:
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void Draw(bool is_indexed, u32 index_offset = 0);
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void Draw(bool is_indexed, u32 index_offset = 0);
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void DispatchDirect();
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void DispatchDirect();
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void DispatchIndirect(VAddr address, u32 offset, u32 size);
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void ScopeMarkerBegin(const std::string_view& str);
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void ScopeMarkerBegin(const std::string_view& str);
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void ScopeMarkerEnd();
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void ScopeMarkerEnd();
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