impl V_CMP_CLASS_F32 common filter masks (#276)
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@ -519,7 +519,38 @@ void Translator::V_CVT_FLR_I32_F32(const GcnInst& inst) {
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}
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void Translator::V_CMP_CLASS_F32(const GcnInst& inst) {
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constexpr u32 SIGNALING_NAN = 1 << 0;
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constexpr u32 QUIET_NAN = 1 << 1;
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constexpr u32 NEGATIVE_INFINITY = 1 << 2;
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constexpr u32 NEGATIVE_NORMAL = 1 << 3;
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constexpr u32 NEGATIVE_DENORM = 1 << 4;
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constexpr u32 NEGATIVE_ZERO = 1 << 5;
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constexpr u32 POSITIVE_ZERO = 1 << 6;
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constexpr u32 POSITIVE_DENORM = 1 << 7;
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constexpr u32 POSITIVE_NORMAL = 1 << 8;
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constexpr u32 POSITIVE_INFINITY = 1 << 9;
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const IR::F32F64 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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if (src1.IsImmediate()) {
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const u32 class_mask = src1.U32();
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IR::U1 value;
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if ((class_mask & (SIGNALING_NAN | QUIET_NAN)) == (SIGNALING_NAN | QUIET_NAN)) {
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value = ir.FPIsNan(src0);
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} else if ((class_mask & (POSITIVE_INFINITY | NEGATIVE_INFINITY)) ==
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(POSITIVE_INFINITY | NEGATIVE_INFINITY)) {
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value = ir.FPIsInf(src0);
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} else {
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UNREACHABLE();
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}
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if (inst.dst[1].field == OperandField::VccLo) {
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return ir.SetVcc(value);
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} else {
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UNREACHABLE();
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}
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} else {
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UNREACHABLE();
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}
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}
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} // namespace Shader::Gcn
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