graphics: separate IRQ for GPU driven flips
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98316575fb
commit
8677972505
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@ -49,10 +49,11 @@ s32 PS4_SYSV_ABI sceGnmAddEqEvent(SceKernelEqueue eq, u64 id, void* udata) {
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kernel_event.event.udata = udata;
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eq->addEvent(kernel_event);
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Platform::IrqC::Instance()->Register([=](Platform::InterruptId irq) {
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Platform::IrqC::Instance()->Register(
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Platform::InterruptId::GfxEop, [=](Platform::InterruptId irq) {
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ASSERT_MSG(irq == Platform::InterruptId::GfxEop,
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"An unexpected IRQ occured"); // We need to conver IRQ# to event id and do proper
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// filtering in trigger function
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"An unexpected IRQ occured"); // We need to conver IRQ# to event id and do
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// proper filtering in trigger function
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eq->triggerEvent(SceKernelEvent::Type::GfxEop, EVFILT_GRAPHICS_CORE, nullptr);
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});
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return ORBIS_OK;
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@ -164,7 +165,7 @@ s32 PS4_SYSV_ABI sceGnmDeleteEqEvent(SceKernelEqueue eq, u64 id) {
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eq->removeEvent(id);
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Platform::IrqC::Instance()->Unregister();
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Platform::IrqC::Instance()->Unregister(Platform::InterruptId::GfxEop);
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return ORBIS_OK;
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}
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@ -223,8 +223,9 @@ s32 sceVideoOutSubmitEopFlip(s32 handle, u32 buf_id, u32 mode, u32 arg, void** u
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return 0x8029000b;
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}
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Platform::IrqC::Instance()->RegisterOnce([=](Platform::InterruptId irq) {
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ASSERT_MSG(irq == Platform::InterruptId::GfxEop, "An unexpected IRQ occured");
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Platform::IrqC::Instance()->RegisterOnce(
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Platform::InterruptId::GfxFlip, [=](Platform::InterruptId irq) {
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ASSERT_MSG(irq == Platform::InterruptId::GfxFlip, "An unexpected IRQ occured");
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const auto result = driver->SubmitFlip(port, buf_id, arg, true);
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ASSERT_MSG(result, "EOP flip submission failed");
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});
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@ -24,52 +24,64 @@ enum class InterruptId : u32 {
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Compute4RelMem = 4u,
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Compute5RelMem = 5u,
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Compute6RelMem = 6u,
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GfxEop = 0x40u
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GfxEop = 7u,
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GfxFlip = 8u
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};
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using IrqHandler = std::function<void(InterruptId)>;
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struct IrqController {
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void RegisterOnce(IrqHandler handler) {
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std::unique_lock lock{m_lock};
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one_time_subscribers.emplace(handler);
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void RegisterOnce(InterruptId irq, IrqHandler handler) {
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ASSERT_MSG(static_cast<u32>(irq) < irq_contexts.size(), "Invalid IRQ number");
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auto& ctx = irq_contexts[static_cast<u32>(irq)];
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std::unique_lock lock{ctx.m_lock};
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ctx.one_time_subscribers.emplace(handler);
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}
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void Register(IrqHandler handler) {
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ASSERT_MSG(!persistent_handler.has_value(),
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void Register(InterruptId irq, IrqHandler handler) {
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ASSERT_MSG(static_cast<u32>(irq) < irq_contexts.size(), "Invalid IRQ number");
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auto& ctx = irq_contexts[static_cast<u32>(irq)];
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ASSERT_MSG(!ctx.persistent_handler.has_value(),
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"Too many persistent handlers"); // Add a slot map if so
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std::unique_lock lock{m_lock};
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persistent_handler.emplace(handler);
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std::unique_lock lock{ctx.m_lock};
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ctx.persistent_handler.emplace(handler);
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}
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void Unregister() {
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std::unique_lock lock{m_lock};
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persistent_handler.reset();
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void Unregister(InterruptId irq) {
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ASSERT_MSG(static_cast<u32>(irq) < irq_contexts.size(), "Invalid IRQ number");
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auto& ctx = irq_contexts[static_cast<u32>(irq)];
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std::unique_lock lock{ctx.m_lock};
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ctx.persistent_handler.reset();
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}
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void Signal(InterruptId irq) {
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std::unique_lock lock{m_lock};
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ASSERT_MSG(static_cast<u32>(irq) < irq_contexts.size(), "Unexpected IRQ signaled");
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auto& ctx = irq_contexts[static_cast<u32>(irq)];
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std::unique_lock lock{ctx.m_lock};
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LOG_TRACE(Core, "IRQ signaled: {}", magic_enum::enum_name(irq));
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if (persistent_handler) {
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persistent_handler.value()(irq);
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if (ctx.persistent_handler) {
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ctx.persistent_handler.value()(irq);
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}
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while (!one_time_subscribers.empty()) {
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const auto& h = one_time_subscribers.front();
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while (!ctx.one_time_subscribers.empty()) {
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const auto& h = ctx.one_time_subscribers.front();
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h(irq);
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one_time_subscribers.pop();
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ctx.one_time_subscribers.pop();
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}
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}
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private:
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struct IrqContext {
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std::optional<IrqHandler> persistent_handler{};
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std::queue<IrqHandler> one_time_subscribers{};
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std::mutex m_lock{};
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};
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std::array<IrqContext, magic_enum::enum_count<InterruptId>()> irq_contexts{};
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};
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using IrqC = Common::Singleton<IrqController>;
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@ -25,8 +25,24 @@ void Liverpool::ProcessCmdList(u32* cmdbuf, u32 size_in_bytes) {
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const PM4ItOpcode opcode = header->type3.opcode;
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const u32 count = header->type3.NumWords();
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switch (opcode) {
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case PM4ItOpcode::Nop:
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case PM4ItOpcode::Nop: {
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const auto* nop = reinterpret_cast<PM4CmdNop*>(header);
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if (nop->header.count.Value() == 0) {
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break;
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}
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switch (nop->data_block[0]) {
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case PM4CmdNop::PayloadType::PatchedFlip: {
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// There is no evidence that GPU CP drives flip events by parsing
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// special NOP packets. For convenience lets assume that it does.
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Platform::IrqC::Instance()->Signal(Platform::InterruptId::GfxFlip);
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break;
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}
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default:
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break;
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}
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break;
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}
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case PM4ItOpcode::SetContextReg: {
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const auto* set_data = reinterpret_cast<PM4CmdSetData*>(header);
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std::memcpy(®s.reg_array[ContextRegWordOffset + set_data->reg_offset],
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