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spirv: Use proper format

This commit is contained in:
IndecisiveTurtle 2024-08-16 19:57:41 +03:00
parent 07169e5fef
commit 7fb811ace5
3 changed files with 11 additions and 7 deletions
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10
src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
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@ -323,7 +323,7 @@ static Id ComponentOffset(EmitContext& ctx, Id address, u32 stride, u32 bit_offs
static Id GetBufferFormatValue(EmitContext& ctx, u32 handle, Id address, u32 comp) { static Id GetBufferFormatValue(EmitContext& ctx, u32 handle, Id address, u32 comp) {
auto& buffer = ctx.buffers[handle]; auto& buffer = ctx.buffers[handle];
const auto format = buffer.buffer.GetDataFmt(); const auto format = buffer.dfmt;
switch (format) { switch (format) {
case AmdGpu::DataFormat::FormatInvalid: case AmdGpu::DataFormat::FormatInvalid:
return ctx.f32_zero_value; return ctx.f32_zero_value;
@ -348,7 +348,7 @@ static Id GetBufferFormatValue(EmitContext& ctx, u32 handle, Id address, u32 com
// uint index = address / 4; // uint index = address / 4;
Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u)); Id index = ctx.OpShiftRightLogical(ctx.U32[1], address, ctx.ConstU32(2u));
const u32 stride = buffer.buffer.GetStride(); const u32 stride = buffer.stride;
if (stride > 4) { if (stride > 4) {
const u32 index_offset = u32(AmdGpu::ComponentOffset(format, comp) / 32); const u32 index_offset = u32(AmdGpu::ComponentOffset(format, comp) / 32);
if (index_offset > 0) { if (index_offset > 0) {
@ -360,7 +360,7 @@ static Id GetBufferFormatValue(EmitContext& ctx, u32 handle, Id address, u32 com
const u32 bit_offset = AmdGpu::ComponentOffset(format, comp) % 32; const u32 bit_offset = AmdGpu::ComponentOffset(format, comp) % 32;
const u32 bit_width = AmdGpu::ComponentBits(format, comp); const u32 bit_width = AmdGpu::ComponentBits(format, comp);
const auto num_format = buffer.buffer.GetNumberFmt(); const auto num_format = buffer.nfmt;
if (num_format == AmdGpu::NumberFormat::Float) { if (num_format == AmdGpu::NumberFormat::Float) {
if (bit_width == 32) { if (bit_width == 32) {
return ctx.OpLoad(ctx.F32[1], ptr); return ctx.OpLoad(ctx.F32[1], ptr);
@ -486,8 +486,8 @@ static Id ConvertF32ToFormat(EmitContext& ctx, Id value, AmdGpu::NumberFormat fo
template <u32 N> template <u32 N>
static void EmitStoreBufferFormatF32xN(EmitContext& ctx, u32 handle, Id address, Id value) { static void EmitStoreBufferFormatF32xN(EmitContext& ctx, u32 handle, Id address, Id value) {
auto& buffer = ctx.buffers[handle]; auto& buffer = ctx.buffers[handle];
const auto format = buffer.buffer.GetDataFmt(); const auto format = buffer.dfmt;
const auto num_format = buffer.buffer.GetNumberFmt(); const auto num_format = buffer.nfmt;
switch (format) { switch (format) {
case AmdGpu::DataFormat::FormatInvalid: case AmdGpu::DataFormat::FormatInvalid:

4
src/shader_recompiler/backend/spirv/spirv_emit_context.cpp
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@ -363,7 +363,9 @@ void EmitContext::DefineBuffers() {
.binding = binding++, .binding = binding++,
.data_types = data_types, .data_types = data_types,
.pointer_type = pointer_type, .pointer_type = pointer_type,
.buffer = buffer.GetVsharp(info), .dfmt = buffer.dfmt,
.nfmt = buffer.nfmt,
.stride = buffer.GetVsharp(info).GetStride(),
}); });
interfaces.push_back(id); interfaces.push_back(id);
i++; i++;

4
src/shader_recompiler/backend/spirv/spirv_emit_context.h
View File

@ -207,7 +207,9 @@ public:
u32 binding; u32 binding;
const VectorIds* data_types; const VectorIds* data_types;
Id pointer_type; Id pointer_type;
AmdGpu::Buffer buffer; AmdGpu::DataFormat dfmt;
AmdGpu::NumberFormat nfmt;
u32 stride;
}; };
u32& binding; u32& binding;