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video_core: Fix some regressions

This commit is contained in:
IndecisiveTurtle 2024-07-01 18:20:19 +03:00
parent 20e83b4d53
commit 7d4f0da40e
5 changed files with 14 additions and 12 deletions
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4
src/core/address_space.cpp
View File

@ -221,8 +221,8 @@ struct AddressSpace::Impl {
void* hint_address = reinterpret_cast<void*>(SYSTEM_MANAGED_MIN);
virtual_size = SystemSize + UserSize;
virtual_base = reinterpret_cast<u8*>(
mmap(reinterpret_cast<void*>(hint_address), virtual_size, PROT_READ | PROT_WRITE,
MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE, -1, 0));
mmap(hint_address, virtual_size, PROT_READ | PROT_WRITE,
MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE | MAP_FIXED, -1, 0));
if (virtual_base == MAP_FAILED) {
LOG_CRITICAL(Kernel_Vmm, "mmap failed: {}", strerror(errno));
throw std::bad_alloc{};

4
src/shader_recompiler/frontend/translate/translate.cpp
View File

@ -197,8 +197,7 @@ void Translator::EmitFetch(const GcnInst& inst) {
// Read the V# of the attribute to figure out component number and type.
const auto buffer = info.ReadUd<AmdGpu::Buffer>(attrib.sgpr_base, attrib.dword_offset);
const u32 num_components = AmdGpu::NumComponents(buffer.data_format);
for (u32 i = 0; i < num_components; i++) {
for (u32 i = 0; i < 4; i++) {
const IR::F32 comp = [&] {
switch (buffer.GetSwizzle(i)) {
case AmdGpu::CompSwizzle::One:
@ -225,6 +224,7 @@ void Translator::EmitFetch(const GcnInst& inst) {
attrib.instance_data);
}
const u32 num_components = AmdGpu::NumComponents(buffer.data_format);
info.vs_inputs.push_back({
.fmt = buffer.num_format,
.binding = attrib.semantic,

5
src/shader_recompiler/ir/passes/resource_tracking_pass.cpp
View File

@ -348,8 +348,9 @@ void PatchImageInstruction(IR::Block& block, IR::Inst& inst, Info& info, Descrip
}
if (inst_info.explicit_lod) {
ASSERT(inst.GetOpcode() == IR::Opcode::ImageFetch ||
inst.GetOpcode() == IR::Opcode::ImageSampleExplicitLod);
const u32 pos = inst.GetOpcode() == IR::Opcode::ImageFetch ? 3 : 2;
inst.GetOpcode() == IR::Opcode::ImageSampleExplicitLod ||
inst.GetOpcode() == IR::Opcode::ImageSampleDrefExplicitLod);
const u32 pos = inst.GetOpcode() == IR::Opcode::ImageSampleExplicitLod ? 2 : 3;
inst.SetArg(pos, arg);
}
}

4
src/video_core/amdgpu/liverpool.h
View File

@ -683,8 +683,8 @@ struct Liverpool {
BitField<0, 5, TilingMode> tile_mode_index;
BitField<5, 5, u32> fmask_tile_mode_index;
BitField<12, 3, u32> num_samples_log2;
BitField<15, 3, u32> num_fragments_log2;
BitField<18, 1, u32> force_dst_alpha_1;
BitField<15, 2, u32> num_fragments_log2;
BitField<17, 1, u32> force_dst_alpha_1;
} attrib;
INSERT_PADDING_WORDS(1);
u32 cmask_base_address;

9
src/video_core/renderer_vulkan/vk_rasterizer.cpp
View File

@ -93,8 +93,9 @@ void Rasterizer::BeginRendering() {
const auto& hint = liverpool->last_cb_extent[col_buf_id];
const auto& image_view = texture_cache.RenderTarget(col_buf, hint);
state.width = std::min<u32>(state.width, hint.width);
state.height = std::min<u32>(state.height, hint.height);
const auto& image = texture_cache.GetImage(image_view.image_id);
state.width = std::min<u32>(state.width, image.info.size.width);
state.height = std::min<u32>(state.height, image.info.size.height);
const bool is_clear = texture_cache.IsMetaCleared(col_buf.CmaskAddress());
state.color_attachments[state.num_color_attachments++] = {
@ -117,8 +118,8 @@ void Rasterizer::BeginRendering() {
const auto& image_view = texture_cache.DepthTarget(regs.depth_buffer, htile_address, hint,
regs.depth_control.depth_write_enable);
const auto& image = texture_cache.GetImage(image_view.image_id);
state.width = std::min<u32>(state.width, hint.width);
state.height = std::min<u32>(state.height, hint.height);
state.width = std::min<u32>(state.width, image.info.size.width);
state.height = std::min<u32>(state.height, image.info.size.height);
state.depth_attachment = {
.imageView = *image_view.image_view,
.imageLayout = image.layout,