shader_recompiler: More image atomics
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e8a2cb7474
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61f18544c7
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@ -79,6 +79,7 @@ Id EmitImageFetch(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id of
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Id ms) {
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const auto& texture = ctx.images[handle & 0xFFFF];
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const Id image = ctx.OpLoad(texture.image_type, texture.id);
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const Id result_type = texture.data_types->Get(4);
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if (Sirit::ValidId(lod)) {
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return ctx.OpImageFetch(ctx.F32[4], image, coords, spv::ImageOperandsMask::Lod, lod);
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} else {
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@ -322,7 +322,17 @@ Id ImageType(EmitContext& ctx, const ImageResource& desc, Id sampled_type) {
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void EmitContext::DefineImagesAndSamplers(const Info& info) {
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for (const auto& image_desc : info.images) {
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const Id sampled_type{image_desc.nfmt == AmdGpu::NumberFormat::Uint ? U32[1] : F32[1]};
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const VectorIds* data_types = [&] {
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switch (image_desc.nfmt) {
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case AmdGpu::NumberFormat::Uint:
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return &U32;
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case AmdGpu::NumberFormat::Sint:
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return &S32;
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default:
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return &F32;
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}
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}();
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const Id sampled_type = data_types->Get(1);
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const Id image_type{ImageType(*this, image_desc, sampled_type)};
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const Id pointer_type{TypePointer(spv::StorageClass::UniformConstant, image_type)};
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const Id id{AddGlobalVariable(pointer_type, spv::StorageClass::UniformConstant)};
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@ -332,6 +342,7 @@ void EmitContext::DefineImagesAndSamplers(const Info& info) {
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image_desc.dword_offset));
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images.push_back({
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.id = id,
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.data_types = data_types,
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.sampled_type = image_desc.is_storage ? sampled_type : TypeSampledImage(image_type),
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.pointer_type = pointer_type,
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.image_type = image_type,
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@ -185,6 +185,7 @@ public:
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struct TextureDefinition {
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Id id;
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const VectorIds* data_types;
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Id sampled_type;
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Id pointer_type;
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Id image_type;
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@ -382,6 +382,33 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::IMAGE_ATOMIC_ADD:
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translator.IMAGE_ATOMIC(AtomicOp::Add, inst);
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break;
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case Opcode::IMAGE_ATOMIC_AND:
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translator.IMAGE_ATOMIC(AtomicOp::And, inst);
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break;
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case Opcode::IMAGE_ATOMIC_OR:
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translator.IMAGE_ATOMIC(AtomicOp::Or, inst);
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break;
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case Opcode::IMAGE_ATOMIC_XOR:
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translator.IMAGE_ATOMIC(AtomicOp::Xor, inst);
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break;
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case Opcode::IMAGE_ATOMIC_UMAX:
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translator.IMAGE_ATOMIC(AtomicOp::Umax, inst);
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break;
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case Opcode::IMAGE_ATOMIC_SMAX:
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translator.IMAGE_ATOMIC(AtomicOp::Smax, inst);
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break;
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case Opcode::IMAGE_ATOMIC_UMIN:
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translator.IMAGE_ATOMIC(AtomicOp::Umin, inst);
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break;
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case Opcode::IMAGE_ATOMIC_SMIN:
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translator.IMAGE_ATOMIC(AtomicOp::Smin, inst);
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break;
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case Opcode::IMAGE_ATOMIC_INC:
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translator.IMAGE_ATOMIC(AtomicOp::Inc, inst);
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break;
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case Opcode::IMAGE_ATOMIC_DEC:
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translator.IMAGE_ATOMIC(AtomicOp::Dec, inst);
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break;
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case Opcode::IMAGE_GET_LOD:
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translator.IMAGE_GET_LOD(inst);
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break;
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@ -590,6 +617,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::V_CVT_I32_F32:
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translator.V_CVT_I32_F32(inst);
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break;
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case Opcode::V_CVT_FLR_I32_F32:
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translator.V_CVT_FLR_I32_F32(inst);
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break;
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case Opcode::V_SUBREV_F32:
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translator.V_SUBREV_F32(inst);
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break;
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@ -153,6 +153,7 @@ public:
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void V_CVT_F32_UBYTE(u32 index, const GcnInst& inst);
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void V_BFREV_B32(const GcnInst& inst);
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void V_LDEXP_F32(const GcnInst& inst);
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void V_CVT_FLR_I32_F32(const GcnInst& inst);
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// Vector Memory
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void BUFFER_LOAD_FORMAT(u32 num_dwords, bool is_typed, const GcnInst& inst);
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@ -508,4 +508,9 @@ void Translator::V_LDEXP_F32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.FPLdexp(src0, src1));
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}
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void Translator::V_CVT_FLR_I32_F32(const GcnInst& inst) {
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const IR::F32 src0{GetSrc(inst.src[0], true)};
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SetDst(inst.dst[0], ir.ConvertFToI(32, true, ir.FPFloor(src0)));
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}
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} // namespace Shader::Gcn
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