ssa_rewrite_pass: Correct phi node type for thread bitmask
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@ -7,7 +7,7 @@
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namespace Shader::Gcn {
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void Translator::EXP(const GcnInst& inst) {
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if (ir.block->has_multiple_predecessors) {
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if (ir.block->has_multiple_predecessors && info.stage == Stage::Fragment) {
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LOG_WARNING(Render_Recompiler, "An ambiguous export appeared in translation");
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ir.Discard(ir.LogicalNot(ir.GetExec()));
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}
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@ -173,7 +173,7 @@ public:
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}
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template <typename Type>
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IR::Value ReadVariable(Type variable, IR::Block* root_block) {
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IR::Value ReadVariable(Type variable, IR::Block* root_block, bool is_thread_bit = false) {
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boost::container::small_vector<ReadState<Type>, 64> stack{
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ReadState<Type>(nullptr),
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ReadState<Type>(root_block),
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@ -201,7 +201,7 @@ public:
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} else if (!block->IsSsaSealed()) {
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// Incomplete CFG
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IR::Inst* phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
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phi->SetFlags(IR::TypeOf(UndefOpcode(variable)));
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phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
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incomplete_phis[block].insert_or_assign(variable, phi);
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stack.back().result = IR::Value{&*phi};
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@ -214,7 +214,7 @@ public:
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} else {
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// Break potential cycles with operandless phi
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IR::Inst* const phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
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phi->SetFlags(IR::TypeOf(UndefOpcode(variable)));
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phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
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WriteVariable(variable, block, IR::Value{phi});
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@ -263,7 +263,8 @@ private:
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template <typename Type>
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IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
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for (IR::Block* const imm_pred : block->ImmPredecessors()) {
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phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred));
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const bool is_thread_bit = std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
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phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
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}
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return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
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}
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@ -346,7 +347,7 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
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case IR::Opcode::GetThreadBitScalarReg:
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case IR::Opcode::GetScalarRegister: {
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const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
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inst.ReplaceUsesWith(pass.ReadVariable(reg, block));
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inst.ReplaceUsesWith(pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
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break;
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}
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case IR::Opcode::GetVectorRegister: {
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