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ssa_rewrite_pass: Correct phi node type for thread bitmask

This commit is contained in:
IndecisiveTurtle 2024-07-15 13:33:57 +03:00
parent ce6a01bd41
commit 58d1cbd9b7
2 changed files with 7 additions and 6 deletions
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2
src/shader_recompiler/frontend/translate/export.cpp
View File

@ -7,7 +7,7 @@
namespace Shader::Gcn { namespace Shader::Gcn {
void Translator::EXP(const GcnInst& inst) { void Translator::EXP(const GcnInst& inst) {
if (ir.block->has_multiple_predecessors) { if (ir.block->has_multiple_predecessors && info.stage == Stage::Fragment) {
LOG_WARNING(Render_Recompiler, "An ambiguous export appeared in translation"); LOG_WARNING(Render_Recompiler, "An ambiguous export appeared in translation");
ir.Discard(ir.LogicalNot(ir.GetExec())); ir.Discard(ir.LogicalNot(ir.GetExec()));
} }

11
src/shader_recompiler/ir/passes/ssa_rewrite_pass.cpp
View File

@ -173,7 +173,7 @@ public:
} }
template <typename Type> template <typename Type>
IR::Value ReadVariable(Type variable, IR::Block* root_block) { IR::Value ReadVariable(Type variable, IR::Block* root_block, bool is_thread_bit = false) {
boost::container::small_vector<ReadState<Type>, 64> stack{ boost::container::small_vector<ReadState<Type>, 64> stack{
ReadState<Type>(nullptr), ReadState<Type>(nullptr),
ReadState<Type>(root_block), ReadState<Type>(root_block),
@ -201,7 +201,7 @@ public:
} else if (!block->IsSsaSealed()) { } else if (!block->IsSsaSealed()) {
// Incomplete CFG // Incomplete CFG
IR::Inst* phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)}; IR::Inst* phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
phi->SetFlags(IR::TypeOf(UndefOpcode(variable))); phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
incomplete_phis[block].insert_or_assign(variable, phi); incomplete_phis[block].insert_or_assign(variable, phi);
stack.back().result = IR::Value{&*phi}; stack.back().result = IR::Value{&*phi};
@ -214,7 +214,7 @@ public:
} else { } else {
// Break potential cycles with operandless phi // Break potential cycles with operandless phi
IR::Inst* const phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)}; IR::Inst* const phi{&*block->PrependNewInst(block->begin(), IR::Opcode::Phi)};
phi->SetFlags(IR::TypeOf(UndefOpcode(variable))); phi->SetFlags(is_thread_bit ? IR::Type::U1 : IR::TypeOf(UndefOpcode(variable)));
WriteVariable(variable, block, IR::Value{phi}); WriteVariable(variable, block, IR::Value{phi});
@ -263,7 +263,8 @@ private:
template <typename Type> template <typename Type>
IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) { IR::Value AddPhiOperands(Type variable, IR::Inst& phi, IR::Block* block) {
for (IR::Block* const imm_pred : block->ImmPredecessors()) { for (IR::Block* const imm_pred : block->ImmPredecessors()) {
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred)); const bool is_thread_bit = std::is_same_v<Type, IR::ScalarReg> && phi.Flags<IR::Type>() == IR::Type::U1;
phi.AddPhiOperand(imm_pred, ReadVariable(variable, imm_pred, is_thread_bit));
} }
return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable)); return TryRemoveTrivialPhi(phi, block, UndefOpcode(variable));
} }
@ -346,7 +347,7 @@ void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
case IR::Opcode::GetThreadBitScalarReg: case IR::Opcode::GetThreadBitScalarReg:
case IR::Opcode::GetScalarRegister: { case IR::Opcode::GetScalarRegister: {
const IR::ScalarReg reg{inst.Arg(0).ScalarReg()}; const IR::ScalarReg reg{inst.Arg(0).ScalarReg()};
inst.ReplaceUsesWith(pass.ReadVariable(reg, block)); inst.ReplaceUsesWith(pass.ReadVariable(reg, block, opcode == IR::Opcode::GetThreadBitScalarReg));
break; break;
} }
case IR::Opcode::GetVectorRegister: { case IR::Opcode::GetVectorRegister: {