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shader_recompiler: More instructions

This commit is contained in:
IndecisiveTurtle 2024-08-04 12:35:40 +03:00
parent a5574bdbf0
commit 5678a2d56c
2 changed files with 20 additions and 0 deletions
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2
src/shader_recompiler/frontend/translate/translate.h
View File

@ -125,6 +125,7 @@ public:
void V_ADD_F32(const GcnInst& inst); void V_ADD_F32(const GcnInst& inst);
void V_CVT_OFF_F32_I4(const GcnInst& inst); void V_CVT_OFF_F32_I4(const GcnInst& inst);
void V_MED3_F32(const GcnInst& inst); void V_MED3_F32(const GcnInst& inst);
void V_MED3_I32(const GcnInst& inst);
void V_FLOOR_F32(const GcnInst& inst); void V_FLOOR_F32(const GcnInst& inst);
void V_SUB_F32(const GcnInst& inst); void V_SUB_F32(const GcnInst& inst);
void V_RCP_F32(const GcnInst& inst); void V_RCP_F32(const GcnInst& inst);
@ -159,6 +160,7 @@ public:
void V_SUB_I32(const GcnInst& inst); void V_SUB_I32(const GcnInst& inst);
void V_LSHR_B32(const GcnInst& inst); void V_LSHR_B32(const GcnInst& inst);
void V_ASHRREV_I32(const GcnInst& inst); void V_ASHRREV_I32(const GcnInst& inst);
void V_ASHR_I32(const GcnInst& inst);
void V_MAD_U32_U24(const GcnInst& inst); void V_MAD_U32_U24(const GcnInst& inst);
void V_RNDNE_F32(const GcnInst& inst); void V_RNDNE_F32(const GcnInst& inst);
void V_BCNT_U32_B32(const GcnInst& inst); void V_BCNT_U32_B32(const GcnInst& inst);

18
src/shader_recompiler/frontend/translate/vector_alu.cpp
View File

@ -24,6 +24,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_LSHR_B32(inst); return V_LSHR_B32(inst);
case Opcode::V_ASHRREV_I32: case Opcode::V_ASHRREV_I32:
return V_ASHRREV_I32(inst); return V_ASHRREV_I32(inst);
case Opcode::V_ASHR_I32:
return V_ASHR_I32(inst);
case Opcode::V_LSHRREV_B32: case Opcode::V_LSHRREV_B32:
return V_LSHRREV_B32(inst); return V_LSHRREV_B32(inst);
case Opcode::V_NOT_B32: case Opcode::V_NOT_B32:
@ -183,6 +185,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_ADD_F32(inst); return V_ADD_F32(inst);
case Opcode::V_MED3_F32: case Opcode::V_MED3_F32:
return V_MED3_F32(inst); return V_MED3_F32(inst);
case Opcode::V_MED3_I32:
return V_MED3_I32(inst);
case Opcode::V_FLOOR_F32: case Opcode::V_FLOOR_F32:
return V_FLOOR_F32(inst); return V_FLOOR_F32(inst);
case Opcode::V_SUB_F32: case Opcode::V_SUB_F32:
@ -479,6 +483,14 @@ void Translator::V_MED3_F32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.FPMax(ir.FPMin(src0, src1), mmx)); SetDst(inst.dst[0], ir.FPMax(ir.FPMin(src0, src1), mmx));
} }
void Translator::V_MED3_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
const IR::U32 src2{GetSrc(inst.src[2])};
const IR::U32 mmx = ir.SMin(ir.SMax(src0, src1), src2);
SetDst(inst.dst[0], ir.SMax(ir.SMin(src0, src1), mmx));
}
void Translator::V_FLOOR_F32(const GcnInst& inst) { void Translator::V_FLOOR_F32(const GcnInst& inst) {
const IR::F32 src0{GetSrc(inst.src[0], true)}; const IR::F32 src0{GetSrc(inst.src[0], true)};
const IR::VectorReg dst_reg{inst.dst[0].code}; const IR::VectorReg dst_reg{inst.dst[0].code};
@ -760,6 +772,12 @@ void Translator::V_ASHRREV_I32(const GcnInst& inst) {
SetDst(inst.dst[0], ir.ShiftRightArithmetic(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F)))); SetDst(inst.dst[0], ir.ShiftRightArithmetic(src1, ir.BitwiseAnd(src0, ir.Imm32(0x1F))));
} }
void Translator::V_ASHR_I32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};
SetDst(inst.dst[0], ir.ShiftRightArithmetic(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
}
void Translator::V_MAD_U32_U24(const GcnInst& inst) { void Translator::V_MAD_U32_U24(const GcnInst& inst) {
V_MAD_I32_I24(inst, false); V_MAD_I32_I24(inst, false);
} }