shader_recompiler: frontend: `SOPC` and `SOPK` handling separated; more cmp opcodes (#634)
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d2e4a200fb
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@ -6,9 +6,17 @@
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namespace Shader::Gcn {
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void Translator::EmitScalarAlu(const GcnInst& inst) {
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switch (inst.encoding) {
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case InstEncoding::SOPC: {
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EmitSOPC(inst);
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break;
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}
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case InstEncoding::SOPK: {
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EmitSOPK(inst);
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break;
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}
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default:
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switch (inst.opcode) {
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case Opcode::S_MOVK_I32:
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return S_MOVK(inst);
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case Opcode::S_MOV_B32:
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return S_MOV(inst);
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case Opcode::S_MUL_I32:
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@ -17,30 +25,6 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
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return S_AND_SAVEEXEC_B64(inst);
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case Opcode::S_MOV_B64:
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return S_MOV_B64(inst);
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case Opcode::S_CMP_LT_U32:
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return S_CMP(ConditionOp::LT, false, inst);
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case Opcode::S_CMP_LE_U32:
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return S_CMP(ConditionOp::LE, false, inst);
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case Opcode::S_CMP_LG_U32:
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return S_CMP(ConditionOp::LG, false, inst);
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case Opcode::S_CMP_LT_I32:
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return S_CMP(ConditionOp::LT, true, inst);
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case Opcode::S_CMP_LG_I32:
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return S_CMP(ConditionOp::LG, true, inst);
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case Opcode::S_CMP_GT_I32:
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return S_CMP(ConditionOp::GT, true, inst);
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case Opcode::S_CMP_LE_I32:
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return S_CMP(ConditionOp::LE, true, inst);
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case Opcode::S_CMP_GE_I32:
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return S_CMP(ConditionOp::GE, true, inst);
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case Opcode::S_CMP_EQ_I32:
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return S_CMP(ConditionOp::EQ, true, inst);
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case Opcode::S_CMP_EQ_U32:
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return S_CMP(ConditionOp::EQ, false, inst);
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case Opcode::S_CMP_GE_U32:
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return S_CMP(ConditionOp::GE, false, inst);
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case Opcode::S_CMP_GT_U32:
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return S_CMP(ConditionOp::GT, false, inst);
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case Opcode::S_OR_B64:
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return S_OR_B64(NegateMode::None, false, inst);
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case Opcode::S_NOR_B64:
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@ -83,10 +67,6 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
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return S_ADD_U32(inst);
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case Opcode::S_ADDC_U32:
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return S_ADDC_U32(inst);
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case Opcode::S_ADDK_I32:
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return S_ADDK_I32(inst);
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case Opcode::S_MULK_I32:
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return S_MULK_I32(inst);
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case Opcode::S_SUB_U32:
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case Opcode::S_SUB_I32:
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return S_SUB_U32(inst);
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@ -96,8 +76,80 @@ void Translator::EmitScalarAlu(const GcnInst& inst) {
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return S_MAX_U32(inst);
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case Opcode::S_WQM_B64:
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break;
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default:
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LogMissingOpcode(inst);
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}
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break;
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}
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}
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void Translator::EmitSOPC(const GcnInst& inst) {
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switch (inst.opcode) {
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case Opcode::S_CMP_EQ_I32:
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return S_CMP(ConditionOp::EQ, true, inst);
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case Opcode::S_CMP_LG_I32:
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return S_CMP(ConditionOp::LG, true, inst);
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case Opcode::S_CMP_GT_I32:
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return S_CMP(ConditionOp::GT, true, inst);
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case Opcode::S_CMP_GE_I32:
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return S_CMP(ConditionOp::GE, true, inst);
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case Opcode::S_CMP_LT_I32:
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return S_CMP(ConditionOp::LT, true, inst);
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case Opcode::S_CMP_LE_I32:
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return S_CMP(ConditionOp::LE, true, inst);
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case Opcode::S_CMP_EQ_U32:
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return S_CMP(ConditionOp::EQ, false, inst);
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case Opcode::S_CMP_LG_U32:
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return S_CMP(ConditionOp::LG, false, inst);
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case Opcode::S_CMP_GT_U32:
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return S_CMP(ConditionOp::GT, false, inst);
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case Opcode::S_CMP_GE_U32:
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return S_CMP(ConditionOp::GE, false, inst);
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case Opcode::S_CMP_LT_U32:
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return S_CMP(ConditionOp::LT, false, inst);
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case Opcode::S_CMP_LE_U32:
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return S_CMP(ConditionOp::LE, false, inst);
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default:
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LogMissingOpcode(inst);
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}
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}
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void Translator::EmitSOPK(const GcnInst& inst) {
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switch (inst.opcode) {
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case Opcode::S_MOVK_I32:
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return S_MOVK(inst);
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case Opcode::S_CMPK_EQ_I32:
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return S_CMPK(ConditionOp::EQ, true, inst);
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case Opcode::S_CMPK_LG_I32:
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return S_CMPK(ConditionOp::LG, true, inst);
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case Opcode::S_CMPK_GT_I32:
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return S_CMPK(ConditionOp::GT, true, inst);
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case Opcode::S_CMPK_GE_I32:
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return S_CMPK(ConditionOp::GE, true, inst);
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case Opcode::S_CMPK_LT_I32:
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return S_CMPK(ConditionOp::LT, true, inst);
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case Opcode::S_CMPK_LE_I32:
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return S_CMPK(ConditionOp::LE, true, inst);
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case Opcode::S_CMPK_EQ_U32:
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return S_CMPK_EQ_U32(inst);
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return S_CMPK(ConditionOp::EQ, false, inst);
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case Opcode::S_CMPK_LG_U32:
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return S_CMPK(ConditionOp::LG, false, inst);
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case Opcode::S_CMPK_GT_U32:
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return S_CMPK(ConditionOp::GT, false, inst);
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case Opcode::S_CMPK_GE_U32:
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return S_CMPK(ConditionOp::GE, false, inst);
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case Opcode::S_CMPK_LT_U32:
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return S_CMPK(ConditionOp::LT, false, inst);
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case Opcode::S_CMPK_LE_U32:
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return S_CMPK(ConditionOp::LE, false, inst);
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case Opcode::S_ADDK_I32:
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return S_ADDK_I32(inst);
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case Opcode::S_MULK_I32:
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return S_MULK_I32(inst);
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default:
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LogMissingOpcode(inst);
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}
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@ -154,6 +206,31 @@ void Translator::S_CMP(ConditionOp cond, bool is_signed, const GcnInst& inst) {
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ir.SetScc(result);
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}
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void Translator::S_CMPK(ConditionOp cond, bool is_signed, const GcnInst& inst) {
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const s32 simm16 = inst.control.sopk.simm;
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const IR::U32 lhs = GetSrc(inst.dst[0]);
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const IR::U32 rhs = ir.Imm32(simm16);
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const IR::U1 result = [&] {
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switch (cond) {
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case ConditionOp::EQ:
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return ir.IEqual(lhs, rhs);
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case ConditionOp::LG:
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return ir.INotEqual(lhs, rhs);
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case ConditionOp::GT:
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return ir.IGreaterThan(lhs, rhs, is_signed);
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case ConditionOp::GE:
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return ir.IGreaterThanEqual(lhs, rhs, is_signed);
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case ConditionOp::LT:
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return ir.ILessThan(lhs, rhs, is_signed);
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case ConditionOp::LE:
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return ir.ILessThanEqual(lhs, rhs, is_signed);
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default:
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UNREACHABLE();
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}
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}();
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ir.SetScc(result);
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}
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void Translator::S_AND_SAVEEXEC_B64(const GcnInst& inst) {
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// This instruction normally operates on 64-bit data (EXEC, VCC, SGPRs)
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// However here we flatten it to 1-bit EXEC and 1-bit VCC. For the destination
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@ -470,11 +547,4 @@ void Translator::S_MIN_U32(const GcnInst& inst) {
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ir.SetScc(ir.IEqual(result, src0));
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}
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void Translator::S_CMPK_EQ_U32(const GcnInst& inst) {
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const s32 simm16 = inst.control.sopk.simm;
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const IR::U32 src0{GetSrc(inst.dst[0])};
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const IR::U32 src1{ir.Imm32(simm16)};
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ir.SetScc(ir.IEqual(src0, src1));
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}
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} // namespace Shader::Gcn
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@ -69,6 +69,10 @@ public:
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void EmitScalarAlu(const GcnInst& inst);
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void EmitVectorAlu(const GcnInst& inst);
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// Instruction encodings
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void EmitSOPC(const GcnInst& inst);
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void EmitSOPK(const GcnInst& inst);
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// Scalar ALU
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void S_MOVK(const GcnInst& inst);
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void S_MOV(const GcnInst& inst);
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@ -98,7 +102,7 @@ public:
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void S_ADDK_I32(const GcnInst& inst);
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void S_MAX_U32(const GcnInst& inst);
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void S_MIN_U32(const GcnInst& inst);
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void S_CMPK_EQ_U32(const GcnInst& inst);
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void S_CMPK(ConditionOp cond, bool is_signed, const GcnInst& inst);
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// Scalar Memory
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void S_LOAD_DWORD(int num_dwords, const GcnInst& inst);
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