Build stabilization (#413)
* shader_recompiler: fix for float convert and debug asserts * libraries: kernel: correct return code on invalid semaphore * amdgpu: additional case for cb extents retrieval heuristic * removed redundant check in assert * amdgpu: fix for linear tiling mode detection fin color buffers * texture_cache: fix for unexpected scheduler flushes by detiler * renderer_vulkan: missing depth barrier * texture_cache: missed slices in rt view; + detiler format
This commit is contained in:
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ace39957ef
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3d0fdf11f0
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@ -174,10 +174,16 @@ s32 PS4_SYSV_ABI sceKernelCreateSema(OrbisKernelSema* sem, const char* pName, u3
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}
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}
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s32 PS4_SYSV_ABI sceKernelWaitSema(OrbisKernelSema sem, s32 needCount, u32* pTimeout) {
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s32 PS4_SYSV_ABI sceKernelWaitSema(OrbisKernelSema sem, s32 needCount, u32* pTimeout) {
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if (!sem) {
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return ORBIS_KERNEL_ERROR_ESRCH;
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}
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return sem->Wait(true, needCount, pTimeout);
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return sem->Wait(true, needCount, pTimeout);
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}
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}
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s32 PS4_SYSV_ABI sceKernelSignalSema(OrbisKernelSema sem, s32 signalCount) {
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s32 PS4_SYSV_ABI sceKernelSignalSema(OrbisKernelSema sem, s32 signalCount) {
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if (!sem) {
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return ORBIS_KERNEL_ERROR_ESRCH;
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}
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if (!sem->Signal(signalCount)) {
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if (!sem->Signal(signalCount)) {
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return ORBIS_KERNEL_ERROR_EINVAL;
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return ORBIS_KERNEL_ERROR_EINVAL;
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}
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}
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@ -185,10 +191,16 @@ s32 PS4_SYSV_ABI sceKernelSignalSema(OrbisKernelSema sem, s32 signalCount) {
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}
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}
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s32 PS4_SYSV_ABI sceKernelPollSema(OrbisKernelSema sem, s32 needCount) {
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s32 PS4_SYSV_ABI sceKernelPollSema(OrbisKernelSema sem, s32 needCount) {
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if (!sem) {
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return ORBIS_KERNEL_ERROR_ESRCH;
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}
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return sem->Wait(false, needCount, nullptr);
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return sem->Wait(false, needCount, nullptr);
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}
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}
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int PS4_SYSV_ABI sceKernelCancelSema(OrbisKernelSema sem, s32 setCount, s32* pNumWaitThreads) {
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int PS4_SYSV_ABI sceKernelCancelSema(OrbisKernelSema sem, s32 setCount, s32* pNumWaitThreads) {
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if (!sem) {
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return ORBIS_KERNEL_ERROR_ESRCH;
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}
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return sem->Cancel(setCount, pNumWaitThreads);
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return sem->Cancel(setCount, pNumWaitThreads);
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}
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}
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@ -386,19 +386,12 @@ static Id GetBufferFormatValue(EmitContext& ctx, u32 handle, Id address, u32 com
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if (is_signed) {
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if (is_signed) {
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value = ctx.OpBitFieldSExtract(ctx.S32[1], value, comp_offset,
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value = ctx.OpBitFieldSExtract(ctx.S32[1], value, comp_offset,
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ctx.ConstU32(bit_width));
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ctx.ConstU32(bit_width));
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value = ctx.OpConvertSToF(ctx.F32[1], value);
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} else {
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} else {
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value = ctx.OpBitFieldUExtract(ctx.U32[1], value, comp_offset,
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value = ctx.OpBitFieldUExtract(ctx.U32[1], value, comp_offset,
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ctx.ConstU32(bit_width));
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ctx.ConstU32(bit_width));
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value = ctx.OpConvertUToF(ctx.F32[1], value);
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}
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} else {
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if (is_signed) {
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value = ctx.OpConvertSToF(ctx.F32[1], value);
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} else {
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value = ctx.OpConvertUToF(ctx.F32[1], value);
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}
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}
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}
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}
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value = ctx.OpBitcast(ctx.F32[1], value);
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return ConvertValue(ctx, value, num_format, bit_width);
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return ConvertValue(ctx, value, num_format, bit_width);
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}
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}
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break;
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break;
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@ -33,14 +33,14 @@ Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id c
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operands.operands);
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operands.operands);
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}
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}
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Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id bias_lc,
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Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod,
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Id offset) {
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Id offset) {
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const auto& texture = ctx.images[handle & 0xFFFF];
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const auto& texture = ctx.images[handle & 0xFFFF];
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const Id image = ctx.OpLoad(texture.image_type, texture.id);
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const Id image = ctx.OpLoad(texture.image_type, texture.id);
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const Id sampler = ctx.OpLoad(ctx.sampler_type, ctx.samplers[handle >> 16]);
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const Id sampler = ctx.OpLoad(ctx.sampler_type, ctx.samplers[handle >> 16]);
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const Id sampled_image = ctx.OpSampledImage(texture.sampled_type, image, sampler);
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const Id sampled_image = ctx.OpSampledImage(texture.sampled_type, image, sampler);
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return ctx.OpImageSampleExplicitLod(ctx.F32[4], sampled_image, coords,
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return ctx.OpImageSampleExplicitLod(ctx.F32[4], sampled_image, coords,
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spv::ImageOperandsMask::Lod, ctx.ConstF32(0.f));
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spv::ImageOperandsMask::Lod, lod);
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}
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}
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Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id dref,
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Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id dref,
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@ -359,7 +359,7 @@ Id EmitConvertU32U16(EmitContext& ctx, Id value);
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Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id bias_lc,
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Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id bias_lc,
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Id offset);
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Id offset);
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Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id bias_lc,
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Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id lod,
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Id offset);
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Id offset);
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Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id dref,
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Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, u32 handle, Id coords, Id dref,
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Id bias_lc, const IR::Value& offset);
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Id bias_lc, const IR::Value& offset);
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@ -376,9 +376,11 @@ s32 TryHandleInlineCbuf(IR::Inst& inst, Info& info, Descriptors& descriptors,
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return -1;
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return -1;
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}
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}
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// We have found this pattern. Build the sharp.
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// We have found this pattern. Build the sharp.
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std::array<u64, 2> buffer;
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std::array<u32, 4> buffer;
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buffer[0] = info.pgm_base + p0->Arg(0).U32() + p0->Arg(1).U32();
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buffer[0] = info.pgm_base + p0->Arg(0).U32() + p0->Arg(1).U32();
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buffer[1] = handle->Arg(2).U32() | handle->Arg(3).U64() << 32;
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buffer[1] = 0;
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buffer[2] = handle->Arg(2).U32();
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buffer[3] = handle->Arg(3).U32();
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cbuf = std::bit_cast<AmdGpu::Buffer>(buffer);
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cbuf = std::bit_cast<AmdGpu::Buffer>(buffer);
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// Assign a binding to this sharp.
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// Assign a binding to this sharp.
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return descriptors.Add(BufferResource{
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return descriptors.Add(BufferResource{
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@ -116,7 +116,7 @@ struct PushData {
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std::array<u8, 32> buf_offsets;
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std::array<u8, 32> buf_offsets;
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void AddOffset(u32 binding, u32 offset) {
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void AddOffset(u32 binding, u32 offset) {
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ASSERT(offset < 64 && binding < 32);
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ASSERT(offset < 256 && binding < buf_offsets.size());
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buf_offsets[binding] = offset;
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buf_offsets[binding] = offset;
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}
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}
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};
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};
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@ -237,7 +237,7 @@ Liverpool::Task Liverpool::ProcessGraphics(std::span<const u32> dcb, std::span<c
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ASSERT(col_buf_id < NumColorBuffers);
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ASSERT(col_buf_id < NumColorBuffers);
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const auto nop_offset = header->type3.count;
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const auto nop_offset = header->type3.count;
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if (nop_offset == 0x0e || nop_offset == 0x0d) {
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if (nop_offset == 0x0e || nop_offset == 0x0d || nop_offset == 0x0b) {
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ASSERT_MSG(payload[nop_offset] == 0xc0001000,
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ASSERT_MSG(payload[nop_offset] == 0xc0001000,
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"NOP hint is missing in CB setup sequence");
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"NOP hint is missing in CB setup sequence");
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last_cb_extent[col_buf_id].raw = payload[nop_offset + 1];
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last_cb_extent[col_buf_id].raw = payload[nop_offset + 1];
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@ -766,7 +766,7 @@ struct Liverpool {
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}
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}
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TilingMode GetTilingMode() const {
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TilingMode GetTilingMode() const {
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return attrib.tile_mode_index;
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return info.linear_general ? TilingMode::Display_Linear : attrib.tile_mode_index;
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}
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}
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bool IsTiled() const {
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bool IsTiled() const {
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@ -146,6 +146,10 @@ public:
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return offset;
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return offset;
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}
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}
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u64 GetFreeSize() const {
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return size_bytes - offset - mapped_size;
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}
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private:
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private:
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struct Watch {
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struct Watch {
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u64 tick{};
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u64 tick{};
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@ -152,7 +152,8 @@ void Rasterizer::BeginRendering() {
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.stencil = regs.stencil_clear}},
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.stencil = regs.stencil_clear}},
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};
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};
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texture_cache.TouchMeta(htile_address, false);
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texture_cache.TouchMeta(htile_address, false);
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state.num_depth_attachments++;
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state.has_depth = true;
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state.has_stencil = image.info.usage.stencil;
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}
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}
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scheduler.BeginRendering(state);
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scheduler.BeginRendering(state);
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}
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}
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@ -38,8 +38,7 @@ void Scheduler::BeginRendering(const RenderState& new_state) {
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.layerCount = 1,
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.layerCount = 1,
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.colorAttachmentCount = render_state.num_color_attachments,
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.colorAttachmentCount = render_state.num_color_attachments,
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.pColorAttachments = render_state.color_attachments.data(),
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.pColorAttachments = render_state.color_attachments.data(),
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.pDepthAttachment =
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.pDepthAttachment = render_state.has_depth ? &render_state.depth_attachment : nullptr,
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render_state.num_depth_attachments ? &render_state.depth_attachment : nullptr,
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};
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};
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current_cmdbuf.beginRendering(rendering_info);
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current_cmdbuf.beginRendering(rendering_info);
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@ -50,6 +49,8 @@ void Scheduler::EndRendering() {
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return;
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return;
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}
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}
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is_rendering = false;
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is_rendering = false;
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current_cmdbuf.endRendering();
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boost::container::static_vector<vk::ImageMemoryBarrier, 9> barriers;
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boost::container::static_vector<vk::ImageMemoryBarrier, 9> barriers;
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for (size_t i = 0; i < render_state.num_color_attachments; ++i) {
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for (size_t i = 0; i < render_state.num_color_attachments; ++i) {
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barriers.push_back(vk::ImageMemoryBarrier{
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barriers.push_back(vk::ImageMemoryBarrier{
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@ -70,10 +71,35 @@ void Scheduler::EndRendering() {
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},
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},
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});
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});
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}
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}
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current_cmdbuf.endRendering();
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if (render_state.has_depth) {
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barriers.push_back(vk::ImageMemoryBarrier{
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.srcAccessMask = vk::AccessFlagBits::eDepthStencilAttachmentWrite,
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.dstAccessMask = vk::AccessFlagBits::eShaderRead | vk::AccessFlagBits::eShaderWrite,
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.oldLayout = render_state.depth_attachment.imageLayout,
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.newLayout = render_state.depth_attachment.imageLayout,
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.srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED,
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.image = render_state.depth_image,
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.subresourceRange =
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{
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.aspectMask = vk::ImageAspectFlagBits::eDepth |
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(render_state.has_stencil ? vk::ImageAspectFlagBits::eStencil
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: vk::ImageAspectFlagBits::eNone),
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.baseMipLevel = 0,
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.levelCount = VK_REMAINING_MIP_LEVELS,
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.baseArrayLayer = 0,
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.layerCount = VK_REMAINING_ARRAY_LAYERS,
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},
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});
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}
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if (!barriers.empty()) {
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if (!barriers.empty()) {
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current_cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eColorAttachmentOutput,
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const auto src_stages =
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vk::PipelineStageFlagBits::eFragmentShader,
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vk::PipelineStageFlagBits::eColorAttachmentOutput |
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(render_state.has_depth ? vk::PipelineStageFlagBits::eLateFragmentTests |
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vk::PipelineStageFlagBits::eEarlyFragmentTests
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: vk::PipelineStageFlagBits::eNone);
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current_cmdbuf.pipelineBarrier(src_stages, vk::PipelineStageFlagBits::eFragmentShader,
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vk::DependencyFlagBits::eByRegion, {}, {}, barriers);
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vk::DependencyFlagBits::eByRegion, {}, {}, barriers);
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}
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}
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}
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}
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@ -20,7 +20,8 @@ struct RenderState {
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vk::RenderingAttachmentInfo depth_attachment{};
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vk::RenderingAttachmentInfo depth_attachment{};
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vk::Image depth_image{};
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vk::Image depth_image{};
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u32 num_color_attachments{};
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u32 num_color_attachments{};
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u32 num_depth_attachments{};
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bool has_depth{};
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bool has_stencil{};
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u32 width = std::numeric_limits<u32>::max();
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u32 width = std::numeric_limits<u32>::max();
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u32 height = std::numeric_limits<u32>::max();
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u32 height = std::numeric_limits<u32>::max();
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@ -189,6 +189,8 @@ ImageInfo::ImageInfo(const AmdGpu::Liverpool::DepthBuffer& buffer, u32 num_slice
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resources.layers = num_slices;
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resources.layers = num_slices;
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meta_info.htile_addr = buffer.z_info.tile_surface_en ? htile_address : 0;
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meta_info.htile_addr = buffer.z_info.tile_surface_en ? htile_address : 0;
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usage.depth_target = true;
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usage.depth_target = true;
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usage.stencil =
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buffer.stencil_info.format != AmdGpu::Liverpool::DepthBuffer::StencilFormat::Invalid;
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guest_address = buffer.Address();
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guest_address = buffer.Address();
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const auto depth_slice_sz = buffer.GetDepthSliceSize();
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const auto depth_slice_sz = buffer.GetDepthSliceSize();
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@ -260,7 +262,7 @@ ImageInfo::ImageInfo(const AmdGpu::Image& image) noexcept {
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case AmdGpu::TilingMode::Display_MacroTiled:
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case AmdGpu::TilingMode::Display_MacroTiled:
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case AmdGpu::TilingMode::Texture_MacroTiled:
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case AmdGpu::TilingMode::Texture_MacroTiled:
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case AmdGpu::TilingMode::Depth_MacroTiled: {
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case AmdGpu::TilingMode::Depth_MacroTiled: {
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// ASSERT(!props.is_cube && !props.is_block);
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ASSERT(!props.is_block);
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ASSERT(num_samples == 1);
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ASSERT(num_samples == 1);
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std::tie(mip_info.pitch, mip_info.size) =
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std::tie(mip_info.pitch, mip_info.size) =
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ImageSizeMacroTiled(mip_w, mip_h, bpp, num_samples, image.tiling_index);
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ImageSizeMacroTiled(mip_w, mip_h, bpp, num_samples, image.tiling_index);
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@ -92,6 +92,8 @@ ImageViewInfo::ImageViewInfo(const AmdGpu::Liverpool::ColorBuffer& col_buffer,
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bool is_vo_surface) noexcept {
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bool is_vo_surface) noexcept {
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const auto base_format =
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const auto base_format =
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Vulkan::LiverpoolToVK::SurfaceFormat(col_buffer.info.format, col_buffer.NumFormat());
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Vulkan::LiverpoolToVK::SurfaceFormat(col_buffer.info.format, col_buffer.NumFormat());
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range.base.layer = col_buffer.view.slice_start;
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range.extent.layers = col_buffer.NumSlices();
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format = Vulkan::LiverpoolToVK::AdjustColorBufferFormat(
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format = Vulkan::LiverpoolToVK::AdjustColorBufferFormat(
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base_format, col_buffer.info.comp_swap.Value(), is_vo_surface);
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base_format, col_buffer.info.comp_swap.Value(), is_vo_surface);
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}
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}
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@ -194,6 +194,7 @@ vk::Format DemoteImageFormatForDetiling(vk::Format format) {
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case vk::Format::eR32G32Sfloat:
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case vk::Format::eR32G32Sfloat:
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case vk::Format::eR32G32Uint:
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case vk::Format::eR32G32Uint:
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case vk::Format::eR16G16B16A16Unorm:
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case vk::Format::eR16G16B16A16Unorm:
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case vk::Format::eR16G16B16A16Sfloat:
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return vk::Format::eR32G32Uint;
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return vk::Format::eR32G32Uint;
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case vk::Format::eBc2SrgbBlock:
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case vk::Format::eBc2SrgbBlock:
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case vk::Format::eBc2UnormBlock:
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case vk::Format::eBc2UnormBlock:
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@ -397,7 +398,7 @@ std::optional<vk::Buffer> TileManager::TryDetile(Image& image) {
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const u32 image_size = image.info.guest_size_bytes;
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const u32 image_size = image.info.guest_size_bytes;
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const auto [in_buffer, in_offset] = [&] -> std::pair<vk::Buffer, u32> {
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const auto [in_buffer, in_offset] = [&] -> std::pair<vk::Buffer, u32> {
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// Use stream buffer for smaller textures.
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// Use stream buffer for smaller textures.
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if (image_size <= StreamBufferSize) {
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if (image_size <= stream_buffer.GetFreeSize()) {
|
||||||
u32 offset = stream_buffer.Copy(image.info.guest_address, image_size);
|
u32 offset = stream_buffer.Copy(image.info.guest_address, image_size);
|
||||||
return {stream_buffer.Handle(), offset};
|
return {stream_buffer.Handle(), offset};
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue