shader_recompiler: added V_TRUNC VOP1/3 (496)
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@ -657,6 +657,9 @@ void Translate(IR::Block* block, std::span<const GcnInst> inst_list, Info& info)
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case Opcode::S_BFM_B32:
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case Opcode::S_BFM_B32:
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translator.S_BFM_B32(inst);
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translator.S_BFM_B32(inst);
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break;
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break;
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case Opcode::V_TRUNC_F32:
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translator.V_TRUNC_F32(inst);
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break;
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case Opcode::S_NOP:
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case Opcode::S_NOP:
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case Opcode::S_CBRANCH_EXECZ:
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case Opcode::S_CBRANCH_EXECZ:
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case Opcode::S_CBRANCH_SCC0:
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case Opcode::S_CBRANCH_SCC0:
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@ -114,6 +114,7 @@ public:
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void V_CVT_I32_F32(const GcnInst& inst);
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void V_CVT_I32_F32(const GcnInst& inst);
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void V_MIN_I32(const GcnInst& inst);
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void V_MIN_I32(const GcnInst& inst);
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void V_MUL_LO_U32(const GcnInst& inst);
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void V_MUL_LO_U32(const GcnInst& inst);
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void V_TRUNC_F32(const GcnInst& inst);
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// Vector Memory
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// Vector Memory
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void BUFFER_LOAD_FORMAT(u32 num_dwords, bool is_typed, const GcnInst& inst);
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void BUFFER_LOAD_FORMAT(u32 num_dwords, bool is_typed, const GcnInst& inst);
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@ -425,4 +425,9 @@ void Translator::V_MUL_LO_U32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.IMul(src0, src1));
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SetDst(inst.dst[0], ir.IMul(src0, src1));
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}
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}
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void Translator::V_TRUNC_F32(const GcnInst& inst) {
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const IR::F32 src0{GetSrc(inst.src[0], true)};
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SetDst(inst.dst[0], ir.FPTrunc(src0));
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}
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} // namespace Shader::Gcn
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} // namespace Shader::Gcn
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