Implement V_LSHL_B64 (#608)
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@ -117,6 +117,7 @@ public:
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void V_AND_B32(const GcnInst& inst);
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void V_AND_B32(const GcnInst& inst);
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void V_LSHLREV_B32(const GcnInst& inst);
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void V_LSHLREV_B32(const GcnInst& inst);
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void V_LSHL_B32(const GcnInst& inst);
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void V_LSHL_B32(const GcnInst& inst);
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void V_LSHL_B64(const GcnInst& inst);
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void V_ADD_I32(const GcnInst& inst);
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void V_ADD_I32(const GcnInst& inst);
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void V_ADDC_U32(const GcnInst& inst);
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void V_ADDC_U32(const GcnInst& inst);
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void V_CVT_F32_I32(const GcnInst& inst);
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void V_CVT_F32_I32(const GcnInst& inst);
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@ -11,6 +11,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return V_LSHLREV_B32(inst);
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return V_LSHLREV_B32(inst);
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case Opcode::V_LSHL_B32:
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case Opcode::V_LSHL_B32:
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return V_LSHL_B32(inst);
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return V_LSHL_B32(inst);
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case Opcode::V_LSHL_B64:
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return V_LSHL_B64(inst);
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case Opcode::V_BFREV_B32:
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case Opcode::V_BFREV_B32:
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return V_BFREV_B32(inst);
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return V_BFREV_B32(inst);
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case Opcode::V_BFE_U32:
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case Opcode::V_BFE_U32:
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@ -390,6 +392,16 @@ void Translator::V_LSHL_B32(const GcnInst& inst) {
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SetDst(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
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SetDst(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm32(0x1F))));
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}
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}
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void Translator::V_LSHL_B64(const GcnInst& inst) {
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const IR::U64 src0{GetSrc64(inst.src[0])};
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const IR::U64 src1{GetSrc64(inst.src[1])};
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const IR::VectorReg dst_reg{inst.dst[0].code};
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ASSERT_MSG(src0.IsImmediate() && src0.U64() == 0 && src1.IsImmediate() && src1.U64() == 0,
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"V_LSHL_B64 with non-zero src0 or src1 is not supported");
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ir.SetVectorReg(dst_reg, ir.Imm32(0));
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ir.SetVectorReg(dst_reg + 1, ir.Imm32(0));
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}
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void Translator::V_ADD_I32(const GcnInst& inst) {
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void Translator::V_ADD_I32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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const IR::U32 src1{ir.GetVectorReg(IR::VectorReg(inst.src[1].code))};
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