recompiler: proper VS inputs initialization
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a75851f7e2
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@ -131,6 +131,13 @@ Id EmitReadConstBufferU32(EmitContext& ctx, u32 handle, Id index) {
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return ctx.OpBitcast(ctx.U32[1], EmitReadConstBuffer(ctx, handle, index));
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}
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Id EmitReadStepRate(EmitContext& ctx, int rate_idx) {
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return ctx.OpLoad(
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ctx.U32[1], ctx.OpAccessChain(ctx.TypePointer(spv::StorageClass::PushConstant, ctx.U32[1]),
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ctx.instance_step_rates,
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rate_idx == 0 ? ctx.u32_zero_value : ctx.u32_one_value));
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}
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Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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if (IR::IsParam(attr)) {
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const u32 index{u32(attr) - u32(IR::Attribute::Param0)};
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@ -149,11 +156,7 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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return ctx.OpLoad(param.component_type, param.id);
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}
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} else {
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const auto rate_idx = param.id.value == 0 ? ctx.u32_zero_value : ctx.u32_one_value;
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const auto step_rate = ctx.OpLoad(
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ctx.U32[1],
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ctx.OpAccessChain(ctx.TypePointer(spv::StorageClass::PushConstant, ctx.U32[1]),
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ctx.instance_step_rates, rate_idx));
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const auto step_rate = EmitReadStepRate(ctx, param.id.value);
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const auto offset = ctx.OpIAdd(
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ctx.U32[1],
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ctx.OpIMul(
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@ -182,6 +185,12 @@ Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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switch (attr) {
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case IR::Attribute::VertexId:
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return ctx.OpLoad(ctx.U32[1], ctx.vertex_index);
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case IR::Attribute::InstanceId:
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return ctx.OpLoad(ctx.U32[1], ctx.instance_id);
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case IR::Attribute::InstanceId0:
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return EmitReadStepRate(ctx, 0);
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case IR::Attribute::InstanceId1:
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return EmitReadStepRate(ctx, 1);
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case IR::Attribute::WorkgroupId:
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return ctx.OpCompositeExtract(ctx.U32[1], ctx.OpLoad(ctx.U32[3], ctx.workgroup_id), comp);
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case IR::Attribute::LocalInvocationId:
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@ -35,10 +35,20 @@ void Translator::EmitPrologue() {
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IR::VectorReg dst_vreg = IR::VectorReg::V0;
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switch (info.stage) {
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case Stage::Vertex:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L146C1-L146C23
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// v0: vertex ID, always present
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::VertexId));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::PrimitiveId));
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// v1: instance ID, step rate 0
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if (info.num_input_vgprs > 0) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId0));
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}
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// v2: instance ID, step rate 1
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if (info.num_input_vgprs > 1) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId1));
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}
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// v3: instance ID, plain
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if (info.num_input_vgprs > 2) {
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ir.SetVectorReg(dst_vreg++, ir.GetAttributeU32(IR::Attribute::InstanceId));
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}
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break;
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case Stage::Fragment:
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// https://github.com/chaotic-cx/mesa-mirror/blob/72326e15/src/amd/vulkan/radv_shader_args.c#L258
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@ -72,6 +72,8 @@ enum class Attribute : u64 {
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LocalInvocationId = 75,
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LocalInvocationIndex = 76,
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FragCoord = 77,
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InstanceId0 = 78, // step rate 0
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InstanceId1 = 79, // step rate 1
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Max,
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};
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@ -163,6 +163,7 @@ struct Info {
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std::array<u32, 3> workgroup_size{};
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u32 num_user_data;
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u32 num_input_vgprs;
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std::span<const u32> user_data;
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Stage stage;
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@ -80,6 +80,7 @@ struct Liverpool {
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union {
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BitField<0, 6, u64> num_vgprs;
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BitField<6, 4, u64> num_sgprs;
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BitField<24, 2, u64> vgpr_comp_cnt; // SPI provided per-thread inputs
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BitField<33, 5, u64> num_user_regs;
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} settings;
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UserData user_data;
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@ -72,6 +72,7 @@ Shader::Info MakeShaderInfo(Shader::Stage stage, std::span<const u32, 16> user_d
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switch (stage) {
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case Shader::Stage::Vertex: {
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info.num_user_data = regs.vs_program.settings.num_user_regs;
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info.num_input_vgprs = regs.vs_program.settings.vgpr_comp_cnt;
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BuildVsOutputs(info, regs.vs_output_control);
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break;
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}
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