Merge pull request #253 from shadps4-emu/graphics/features_and_fixes
Graphics: missing features and fixes
This commit is contained in:
commit
189033ae24
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@ -3,6 +3,7 @@
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#include "common/assert.h"
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#include "common/config.h"
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#include "common/debug.h"
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#include "common/logging/log.h"
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#include "common/path_util.h"
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#include "common/slot_vector.h"
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@ -264,6 +265,7 @@ static_assert(CtxInitSequence400.size() == 0x61);
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// In case if `submitDone` is issued we need to block submissions until GPU idle
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static u32 submission_lock{};
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std::condition_variable cv_lock{};
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static std::mutex m_submission{};
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static u64 frames_submitted{}; // frame counter
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static bool send_init_packet{true}; // initialize HW state before first game's submit in a frame
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@ -277,6 +279,18 @@ struct AscQueueInfo {
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static Common::SlotVector<AscQueueInfo> asc_queues{};
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static constexpr VAddr tessellation_factors_ring_addr = 0xFF0000000ULL;
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static void ResetSubmissionLock(Platform::InterruptId irq) {
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std::unique_lock lock{m_submission};
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submission_lock = 0;
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cv_lock.notify_all();
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}
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static void WaitGpuIdle() {
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HLE_TRACE;
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std::unique_lock lock{m_submission};
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cv_lock.wait(lock, [] { return submission_lock == 0; });
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}
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static void DumpCommandList(std::span<const u32> cmd_list, const std::string& postfix) {
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using namespace Common::FS;
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const auto dump_dir = GetUserPath(PathType::PM4Dir);
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@ -465,14 +479,9 @@ void PS4_SYSV_ABI sceGnmDingDong(u32 gnm_vqid, u32 next_offs_dw) {
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return;
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}
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std::unique_lock lock{m_submission};
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if (submission_lock != 0) {
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liverpool->WaitGpuIdle();
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WaitGpuIdle();
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// Suspend logic goes here
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submission_lock = 0;
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}
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/* Suspend logic goes here */
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auto vqid = gnm_vqid - 1;
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auto& asc_queue = asc_queues[{vqid}];
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@ -863,9 +872,9 @@ int PS4_SYSV_ABI sceGnmEndWorkload() {
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return ORBIS_OK;
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}
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int PS4_SYSV_ABI sceGnmFindResourcesPublic() {
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LOG_ERROR(Lib_GnmDriver, "(STUBBED) called");
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return ORBIS_OK;
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s32 PS4_SYSV_ABI sceGnmFindResourcesPublic() {
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LOG_TRACE(Lib_GnmDriver, "called");
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return ORBIS_GNM_ERROR_FAILURE; // not available in retail FW
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}
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void PS4_SYSV_ABI sceGnmFlushGarlic() {
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@ -1321,7 +1330,7 @@ s32 PS4_SYSV_ABI sceGnmSetEmbeddedPsShader(u32* cmdbuf, u32 size, u32 shader_id,
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if (shader_id > 1) {
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LOG_ERROR(Lib_GnmDriver, "Unknown shader id {}", shader_id);
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return 0x8eee00ff;
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return ORBIS_GNM_ERROR_FAILURE;
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}
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// clang-format off
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@ -1391,7 +1400,7 @@ s32 PS4_SYSV_ABI sceGnmSetEmbeddedVsShader(u32* cmdbuf, u32 size, u32 shader_id,
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if (shader_id != 0) {
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LOG_ERROR(Lib_GnmDriver, "Unknown shader id {}", shader_id);
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return 0x8eee00ff;
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return ORBIS_GNM_ERROR_FAILURE;
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}
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// A fullscreen triangle with one uv set
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@ -1930,13 +1939,9 @@ s32 PS4_SYSV_ABI sceGnmSubmitCommandBuffers(u32 count, const u32* dcb_gpu_addrs[
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}
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}
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if (submission_lock != 0) {
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liverpool->WaitGpuIdle();
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WaitGpuIdle();
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// Suspend logic goes here
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submission_lock = 0;
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}
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/* Suspend logic goes here */
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if (send_init_packet) {
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if (sdk_version <= 0x1ffffffu) {
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@ -1990,7 +1995,6 @@ int PS4_SYSV_ABI sceGnmSubmitDone() {
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if (!liverpool->IsGpuIdle()) {
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submission_lock = true;
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}
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liverpool->NotifySubmitDone();
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send_init_packet = true;
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++frames_submitted;
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return ORBIS_OK;
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@ -2471,6 +2475,9 @@ void RegisterlibSceGnmDriver(Core::Loader::SymbolsResolver* sym) {
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sdk_version = 0;
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}
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Platform::IrqC::Instance()->Register(Platform::InterruptId::GpuIdle, ResetSubmissionLock,
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nullptr);
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LIB_FUNCTION("b0xyllnVY-I", "libSceGnmDriver", 1, "libSceGnmDriver", 1, 1, sceGnmAddEqEvent);
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LIB_FUNCTION("b08AgtPlHPg", "libSceGnmDriver", 1, "libSceGnmDriver", 1, 1,
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sceGnmAreSubmitsAllowed);
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@ -75,7 +75,7 @@ int PS4_SYSV_ABI sceGnmDriverInternalVirtualQuery();
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int PS4_SYSV_ABI sceGnmDriverTraceInProgress();
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int PS4_SYSV_ABI sceGnmDriverTriggerCapture();
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int PS4_SYSV_ABI sceGnmEndWorkload();
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int PS4_SYSV_ABI sceGnmFindResourcesPublic();
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s32 PS4_SYSV_ABI sceGnmFindResourcesPublic();
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void PS4_SYSV_ABI sceGnmFlushGarlic();
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int PS4_SYSV_ABI sceGnmGetCoredumpAddress();
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int PS4_SYSV_ABI sceGnmGetCoredumpMode();
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@ -26,6 +26,7 @@ enum class InterruptId : u32 {
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Compute6RelMem = 6u,
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GfxEop = 7u,
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GfxFlip = 8u,
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GpuIdle = 9u,
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};
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using IrqHandler = std::function<void(InterruptId)>;
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@ -135,16 +135,34 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp) {
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if (IR::IsParam(attr)) {
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const u32 index{u32(attr) - u32(IR::Attribute::Param0)};
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const auto& param{ctx.input_params.at(index)};
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if (param.buffer_handle < 0) {
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if (!ValidId(param.id)) {
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// Attribute is disabled or varying component is not written
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return ctx.ConstF32(comp == 3 ? 1.0f : 0.0f);
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}
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if (param.num_components > 1) {
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const Id pointer{ctx.OpAccessChain(param.pointer_type, param.id, ctx.ConstU32(comp))};
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const Id pointer{
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ctx.OpAccessChain(param.pointer_type, param.id, ctx.ConstU32(comp))};
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return ctx.OpLoad(param.component_type, pointer);
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} else {
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return ctx.OpLoad(param.component_type, param.id);
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}
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} else {
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const auto rate_idx = param.id.value == 0 ? ctx.u32_zero_value : ctx.u32_one_value;
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const auto step_rate = ctx.OpLoad(
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ctx.U32[1],
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ctx.OpAccessChain(ctx.TypePointer(spv::StorageClass::PushConstant, ctx.U32[1]),
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ctx.instance_step_rates, rate_idx));
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const auto offset = ctx.OpIAdd(
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ctx.U32[1],
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ctx.OpIMul(
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ctx.U32[1],
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ctx.OpUDiv(ctx.U32[1], ctx.OpLoad(ctx.U32[1], ctx.instance_id), step_rate),
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ctx.ConstU32(param.num_components)),
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ctx.ConstU32(comp));
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return EmitReadConstBuffer(ctx, param.buffer_handle, offset);
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}
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}
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switch (attr) {
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case IR::Attribute::FragCoord: {
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@ -171,17 +171,47 @@ Id MakeDefaultValue(EmitContext& ctx, u32 default_value) {
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void EmitContext::DefineInputs(const Info& info) {
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switch (stage) {
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case Stage::Vertex:
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case Stage::Vertex: {
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vertex_index = DefineVariable(U32[1], spv::BuiltIn::VertexIndex, spv::StorageClass::Input);
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base_vertex = DefineVariable(U32[1], spv::BuiltIn::BaseVertex, spv::StorageClass::Input);
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instance_id = DefineVariable(U32[1], spv::BuiltIn::InstanceIndex, spv::StorageClass::Input);
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// Create push constants block for instance steps rates
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const Id struct_type{Name(TypeStruct(U32[1], U32[1]), "instance_step_rates")};
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Decorate(struct_type, spv::Decoration::Block);
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MemberName(struct_type, 0, "sr0");
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MemberName(struct_type, 1, "sr1");
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MemberDecorate(struct_type, 0, spv::Decoration::Offset, 0U);
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MemberDecorate(struct_type, 1, spv::Decoration::Offset, 4U);
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instance_step_rates = DefineVar(struct_type, spv::StorageClass::PushConstant);
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Name(instance_step_rates, "step_rates");
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interfaces.push_back(instance_step_rates);
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for (const auto& input : info.vs_inputs) {
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const Id type{GetAttributeType(*this, input.fmt)};
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const Id id{DefineInput(type, input.binding)};
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if (input.instance_step_rate == Info::VsInput::InstanceIdType::OverStepRate0 ||
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input.instance_step_rate == Info::VsInput::InstanceIdType::OverStepRate1) {
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const u32 rate_idx =
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input.instance_step_rate == Info::VsInput::InstanceIdType::OverStepRate0 ? 0
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: 1;
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// Note that we pass index rather than Id
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input_params[input.binding] = {
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rate_idx, input_u32, U32[1], input.num_components, input.instance_data_buf,
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};
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} else {
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Id id{DefineInput(type, input.binding)};
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if (input.instance_step_rate == Info::VsInput::InstanceIdType::Plain) {
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Name(id, fmt::format("vs_instance_attr{}", input.binding));
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} else {
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Name(id, fmt::format("vs_in_attr{}", input.binding));
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}
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input_params[input.binding] = GetAttributeInfo(input.fmt, id);
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interfaces.push_back(id);
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}
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}
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break;
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}
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case Stage::Fragment:
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if (info.uses_group_quad) {
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subgroup_local_invocation_id = DefineVariable(
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@ -276,7 +306,10 @@ void EmitContext::DefineBuffers(const Info& info) {
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if (std::ranges::find(type_ids, record_array_type.value, &Id::value) == type_ids.end()) {
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Decorate(record_array_type, spv::Decoration::ArrayStride, 4);
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const auto name =
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fmt::format("{}_cbuf_block_{}{}", stage, 'f', sizeof(float) * CHAR_BIT);
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buffer.is_instance_data
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? fmt::format("{}_instance_data{}_{}{}", stage, i, 'f',
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sizeof(float) * CHAR_BIT)
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: fmt::format("{}_cbuf_block_{}{}", stage, 'f', sizeof(float) * CHAR_BIT);
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Name(struct_type, name);
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Decorate(struct_type, spv::Decoration::Block);
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MemberName(struct_type, 0, "data");
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@ -317,6 +350,14 @@ spv::ImageFormat GetFormat(const AmdGpu::Image& image) {
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image.GetNumberFmt() == AmdGpu::NumberFormat::Float) {
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return spv::ImageFormat::Rg32f;
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}
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format32_32 &&
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image.GetNumberFmt() == AmdGpu::NumberFormat::Uint) {
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return spv::ImageFormat::Rg32ui;
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}
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format32_32_32_32 &&
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image.GetNumberFmt() == AmdGpu::NumberFormat::Uint) {
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return spv::ImageFormat::Rgba32ui;
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}
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if (image.GetDataFmt() == AmdGpu::DataFormat::Format16 &&
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image.GetNumberFmt() == AmdGpu::NumberFormat::Float) {
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return spv::ImageFormat::R16f;
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@ -165,6 +165,8 @@ public:
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Id output_position{};
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Id vertex_index{};
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Id instance_id{};
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Id instance_step_rates{};
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Id base_vertex{};
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Id frag_coord{};
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Id front_facing{};
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@ -214,6 +216,7 @@ public:
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Id pointer_type;
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Id component_type;
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u32 num_components;
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s32 buffer_handle{-1};
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};
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std::array<SpirvAttribute, 32> input_params{};
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std::array<SpirvAttribute, 32> output_params{};
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@ -235,9 +235,22 @@ void Translator::EmitFetch(const GcnInst& inst) {
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ir.SetVectorReg(dst_reg++, comp);
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}
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if (attrib.instance_data == 2 || attrib.instance_data == 3) {
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LOG_WARNING(Render_Recompiler, "Unsupported instance step rate = {}",
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attrib.instance_data);
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// In case of programmable step rates we need to fallback to instance data pulling in
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// shader, so VBs should be bound as regular data buffers
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s32 instance_buf_handle = -1;
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const auto step_rate = static_cast<Info::VsInput::InstanceIdType>(attrib.instance_data);
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if (step_rate == Info::VsInput::OverStepRate0 ||
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step_rate == Info::VsInput::OverStepRate1) {
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info.buffers.push_back({
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.sgpr_base = attrib.sgpr_base,
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.dword_offset = attrib.dword_offset,
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.stride = buffer.GetStride(),
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.num_records = buffer.num_records,
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.used_types = IR::Type::F32,
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.is_storage = true, // we may not fit into UBO with large meshes
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.is_instance_data = true,
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});
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instance_buf_handle = s32(info.buffers.size() - 1);
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}
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const u32 num_components = AmdGpu::NumComponents(buffer.GetDataFmt());
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@ -247,7 +260,8 @@ void Translator::EmitFetch(const GcnInst& inst) {
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.num_components = std::min<u16>(attrib.num_elements, num_components),
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.sgpr_base = attrib.sgpr_base,
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.dword_offset = attrib.dword_offset,
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.instance_step_rate = static_cast<Info::VsInput::InstanceIdType>(attrib.instance_data),
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.instance_step_rate = step_rate,
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.instance_data_buf = instance_buf_handle,
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});
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}
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}
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@ -165,13 +165,14 @@ void Translator::IMAGE_GATHER(const GcnInst& inst) {
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if (!flags.test(MimgModifier::Pcf)) {
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return ir.ImageGather(handle, body, offset, {}, info);
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}
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ASSERT(mimg.dmask & 1); // should be always 1st (R) component
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return ir.ImageGatherDref(handle, body, offset, {}, dref, info);
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}();
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// For gather4 instructions dmask selects which component to read and must have
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// only one bit set to 1
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ASSERT_MSG(std::popcount(mimg.dmask) == 1, "Unexpected bits in gather dmask");
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for (u32 i = 0; i < 4; i++) {
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if (((mimg.dmask >> i) & 1) == 0) {
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continue;
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}
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const IR::F32 value = IR::F32{ir.CompositeExtract(texel, i)};
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ir.SetVectorReg(dest_reg++, value);
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}
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|
|
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@ -77,7 +77,8 @@ struct BufferResource {
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u32 num_records;
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IR::Type used_types;
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AmdGpu::Buffer inline_cbuf;
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bool is_storage;
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bool is_storage{false};
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bool is_instance_data{false};
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constexpr AmdGpu::Buffer GetVsharp(const Info& info) const noexcept;
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};
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|
@ -116,6 +117,7 @@ struct Info {
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u8 sgpr_base;
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u8 dword_offset;
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InstanceIdType instance_step_rate;
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s32 instance_data_buf;
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};
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boost::container::static_vector<VsInput, 32> vs_inputs{};
|
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|
||||
|
|
|
@ -66,19 +66,8 @@ void Liverpool::Process(std::stop_token stoken) {
|
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}
|
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}
|
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|
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if (submit_done) {
|
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std::scoped_lock lk{submit_mutex};
|
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submit_cv.notify_all();
|
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submit_done = false;
|
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Platform::IrqC::Instance()->Signal(Platform::InterruptId::GpuIdle);
|
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}
|
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}
|
||||
}
|
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|
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void Liverpool::WaitGpuIdle() {
|
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RENDERER_TRACE;
|
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|
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std::unique_lock lk{submit_mutex};
|
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submit_cv.wait(lk, [this] { return num_submits == 0; });
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}
|
||||
|
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Liverpool::Task Liverpool::ProcessCeUpdate(std::span<const u32> ccb) {
|
||||
|
|
|
@ -887,7 +887,10 @@ struct Liverpool {
|
|||
IndexBufferType index_buffer_type;
|
||||
INSERT_PADDING_WORDS(0xA2A1 - 0xA29E - 2);
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u32 enable_primitive_id;
|
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INSERT_PADDING_WORDS(0xA2DF - 0xA2A1 - 1);
|
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INSERT_PADDING_WORDS(0xA2A8 - 0xA2A1 - 1);
|
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u32 vgt_instance_step_rate_0;
|
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u32 vgt_instance_step_rate_1;
|
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INSERT_PADDING_WORDS(0xA2DF - 0xA2A9 - 1);
|
||||
PolygonOffset poly_offset;
|
||||
INSERT_PADDING_WORDS(0xA2F8 - 0xA2DF - 5);
|
||||
AaConfig aa_config;
|
||||
|
@ -937,18 +940,10 @@ public:
|
|||
void SubmitGfx(std::span<const u32> dcb, std::span<const u32> ccb);
|
||||
void SubmitAsc(u32 vqid, std::span<const u32> acb);
|
||||
|
||||
void WaitGpuIdle();
|
||||
|
||||
bool IsGpuIdle() const {
|
||||
return num_submits == 0;
|
||||
}
|
||||
|
||||
void NotifySubmitDone() {
|
||||
std::scoped_lock lk{submit_mutex};
|
||||
submit_done = true;
|
||||
submit_cv.notify_all();
|
||||
}
|
||||
|
||||
void BindRasterizer(Vulkan::Rasterizer* rasterizer_) {
|
||||
rasterizer = rasterizer_;
|
||||
}
|
||||
|
@ -1017,7 +1012,6 @@ private:
|
|||
u32 num_submits{};
|
||||
std::mutex submit_mutex;
|
||||
std::condition_variable_any submit_cv;
|
||||
std::atomic<bool> submit_done{};
|
||||
};
|
||||
|
||||
static_assert(GFX6_3D_REG_INDEX(ps_program) == 0x2C08);
|
||||
|
@ -1055,6 +1049,8 @@ static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
|
|||
static_assert(GFX6_3D_REG_INDEX(index_size) == 0xA29D);
|
||||
static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
|
||||
static_assert(GFX6_3D_REG_INDEX(enable_primitive_id) == 0xA2A1);
|
||||
static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_0) == 0xA2A8);
|
||||
static_assert(GFX6_3D_REG_INDEX(vgt_instance_step_rate_1) == 0xA2A9);
|
||||
static_assert(GFX6_3D_REG_INDEX(poly_offset) == 0xA2DF);
|
||||
static_assert(GFX6_3D_REG_INDEX(aa_config) == 0xA2F8);
|
||||
static_assert(GFX6_3D_REG_INDEX(color_buffers[0].base_address) == 0xA318);
|
||||
|
|
|
@ -321,6 +321,9 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
|
|||
if (data_format == AmdGpu::DataFormat::FormatBc4 && num_format == AmdGpu::NumberFormat::Unorm) {
|
||||
return vk::Format::eBc4UnormBlock;
|
||||
}
|
||||
if (data_format == AmdGpu::DataFormat::FormatBc5 && num_format == AmdGpu::NumberFormat::Unorm) {
|
||||
return vk::Format::eBc5UnormBlock;
|
||||
}
|
||||
if (data_format == AmdGpu::DataFormat::Format16_16_16_16 &&
|
||||
num_format == AmdGpu::NumberFormat::Sint) {
|
||||
return vk::Format::eR16G16B16A16Sint;
|
||||
|
@ -366,6 +369,9 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
|
|||
if (data_format == AmdGpu::DataFormat::Format8_8 && num_format == AmdGpu::NumberFormat::Unorm) {
|
||||
return vk::Format::eR8G8Unorm;
|
||||
}
|
||||
if (data_format == AmdGpu::DataFormat::Format8_8 && num_format == AmdGpu::NumberFormat::Snorm) {
|
||||
return vk::Format::eR8G8Snorm;
|
||||
}
|
||||
if (data_format == AmdGpu::DataFormat::FormatBc7 && num_format == AmdGpu::NumberFormat::Unorm) {
|
||||
return vk::Format::eBc7UnormBlock;
|
||||
}
|
||||
|
@ -429,6 +435,10 @@ vk::Format SurfaceFormat(AmdGpu::DataFormat data_format, AmdGpu::NumberFormat nu
|
|||
if (data_format == AmdGpu::DataFormat::Format16 && num_format == AmdGpu::NumberFormat::Unorm) {
|
||||
return vk::Format::eR16Unorm;
|
||||
}
|
||||
if (data_format == AmdGpu::DataFormat::Format16_16_16_16 &&
|
||||
num_format == AmdGpu::NumberFormat::Unorm) {
|
||||
return vk::Format::eR16G16B16A16Unorm;
|
||||
}
|
||||
UNREACHABLE_MSG("Unknown data_format={} and num_format={}", u32(data_format), u32(num_format));
|
||||
}
|
||||
|
||||
|
|
|
@ -30,12 +30,19 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
|
|||
stages[i] = *infos[i];
|
||||
}
|
||||
BuildDescSetLayout();
|
||||
|
||||
const vk::PushConstantRange push_constants = {
|
||||
.stageFlags = vk::ShaderStageFlagBits::eVertex,
|
||||
.offset = 0,
|
||||
.size = 2 * sizeof(u32),
|
||||
};
|
||||
|
||||
const vk::DescriptorSetLayout set_layout = *desc_layout;
|
||||
const vk::PipelineLayoutCreateInfo layout_info = {
|
||||
.setLayoutCount = 1U,
|
||||
.pSetLayouts = &set_layout,
|
||||
.pushConstantRangeCount = 0,
|
||||
.pPushConstantRanges = nullptr,
|
||||
.pushConstantRangeCount = 1,
|
||||
.pPushConstantRanges = &push_constants,
|
||||
};
|
||||
pipeline_layout = instance.GetDevice().createPipelineLayoutUnique(layout_info);
|
||||
|
||||
|
@ -43,6 +50,12 @@ GraphicsPipeline::GraphicsPipeline(const Instance& instance_, Scheduler& schedul
|
|||
boost::container::static_vector<vk::VertexInputAttributeDescription, 32> attributes;
|
||||
const auto& vs_info = stages[0];
|
||||
for (const auto& input : vs_info.vs_inputs) {
|
||||
if (input.instance_step_rate == Shader::Info::VsInput::InstanceIdType::OverStepRate0 ||
|
||||
input.instance_step_rate == Shader::Info::VsInput::InstanceIdType::OverStepRate1) {
|
||||
// Skip attribute binding as the data will be pulled by shader
|
||||
continue;
|
||||
}
|
||||
|
||||
const auto buffer = vs_info.ReadUd<AmdGpu::Buffer>(input.sgpr_base, input.dword_offset);
|
||||
attributes.push_back({
|
||||
.location = input.binding,
|
||||
|
@ -420,6 +433,11 @@ void GraphicsPipeline::BindVertexBuffers(StreamBuffer& staging) const {
|
|||
// Calculate buffers memory overlaps
|
||||
boost::container::static_vector<BufferRange, MaxVertexBufferCount> ranges{};
|
||||
for (const auto& input : vs_info.vs_inputs) {
|
||||
if (input.instance_step_rate == Shader::Info::VsInput::InstanceIdType::OverStepRate0 ||
|
||||
input.instance_step_rate == Shader::Info::VsInput::InstanceIdType::OverStepRate1) {
|
||||
continue;
|
||||
}
|
||||
|
||||
const auto& buffer = vs_info.ReadUd<AmdGpu::Buffer>(input.sgpr_base, input.dword_offset);
|
||||
if (buffer.GetSize() == 0) {
|
||||
continue;
|
||||
|
|
|
@ -67,20 +67,24 @@ public:
|
|||
void BindResources(Core::MemoryManager* memory, StreamBuffer& staging,
|
||||
VideoCore::TextureCache& texture_cache) const;
|
||||
|
||||
[[nodiscard]] vk::Pipeline Handle() const noexcept {
|
||||
vk::Pipeline Handle() const noexcept {
|
||||
return *pipeline;
|
||||
}
|
||||
|
||||
[[nodiscard]] bool IsEmbeddedVs() const noexcept {
|
||||
vk::PipelineLayout GetLayout() const {
|
||||
return *pipeline_layout;
|
||||
}
|
||||
|
||||
bool IsEmbeddedVs() const noexcept {
|
||||
static constexpr size_t EmbeddedVsHash = 0x9b2da5cf47f8c29f;
|
||||
return key.stage_hashes[0] == EmbeddedVsHash;
|
||||
}
|
||||
|
||||
[[nodiscard]] auto GetWriteMasks() const {
|
||||
auto GetWriteMasks() const {
|
||||
return key.write_masks;
|
||||
}
|
||||
|
||||
[[nodiscard]] bool IsDepthEnabled() const {
|
||||
bool IsDepthEnabled() const {
|
||||
return key.depth.depth_enable.Value();
|
||||
}
|
||||
|
||||
|
|
|
@ -183,7 +183,7 @@ void PipelineCache::RefreshGraphicsKey() {
|
|||
int remapped_cb{};
|
||||
for (auto cb = 0u; cb < Liverpool::NumColorBuffers; ++cb) {
|
||||
auto const& col_buf = regs.color_buffers[cb];
|
||||
if (!col_buf || skip_cb_binding) {
|
||||
if (skip_cb_binding || !col_buf || !regs.color_target_mask.GetMask(cb)) {
|
||||
continue;
|
||||
}
|
||||
const auto base_format =
|
||||
|
|
|
@ -54,6 +54,13 @@ void Rasterizer::Draw(bool is_indexed, u32 index_offset) {
|
|||
UpdateDynamicState(*pipeline);
|
||||
|
||||
cmdbuf.bindPipeline(vk::PipelineBindPoint::eGraphics, pipeline->Handle());
|
||||
|
||||
const u32 step_rates[] = {
|
||||
regs.vgt_instance_step_rate_0,
|
||||
regs.vgt_instance_step_rate_1,
|
||||
};
|
||||
cmdbuf.pushConstants(pipeline->GetLayout(), vk::ShaderStageFlagBits::eVertex, 0u,
|
||||
sizeof(step_rates), &step_rates);
|
||||
if (is_indexed) {
|
||||
cmdbuf.drawIndexed(num_indices, regs.num_instances.NumInstances(), 0, 0, 0);
|
||||
} else {
|
||||
|
@ -99,6 +106,12 @@ void Rasterizer::BeginRendering() {
|
|||
continue;
|
||||
}
|
||||
|
||||
// If the color buffer is still bound but rendering to it is disabled by the target mask,
|
||||
// we need to prevent the render area from being affected by unbound render target extents.
|
||||
if (!regs.color_target_mask.GetMask(col_buf_id)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
const auto& hint = liverpool->last_cb_extent[col_buf_id];
|
||||
const auto& image_view = texture_cache.RenderTarget(col_buf, hint);
|
||||
const auto& image = texture_cache.GetImage(image_view.image_id);
|
||||
|
|
|
@ -189,10 +189,14 @@ vk::Format DemoteImageFormatForDetiling(vk::Format format) {
|
|||
case vk::Format::eR32Uint:
|
||||
return vk::Format::eR32Uint;
|
||||
case vk::Format::eBc1RgbaUnormBlock:
|
||||
case vk::Format::eBc4UnormBlock:
|
||||
case vk::Format::eR32G32Sfloat:
|
||||
return vk::Format::eR32G32Uint;
|
||||
case vk::Format::eBc2SrgbBlock:
|
||||
case vk::Format::eBc2UnormBlock:
|
||||
case vk::Format::eBc3SrgbBlock:
|
||||
case vk::Format::eBc3UnormBlock:
|
||||
case vk::Format::eBc5UnormBlock:
|
||||
case vk::Format::eBc7SrgbBlock:
|
||||
case vk::Format::eBc7UnormBlock:
|
||||
return vk::Format::eR32G32B32A32Uint;
|
||||
|
|
Loading…
Reference in New Issue